cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Observer
Observer
7,175 Views
Registered: ‎11-11-2009

mutiple clock frequencies in FPGA

Hi

 

Are there are any means to get mutiple clock frequencies from FPGA, which runs on system clock?

 

Are there any blocks in XSG to achieve above directly?

 

Hope Xilinx employees are other experts can help us

 

 

regards

selvam

8 Replies
Highlighted
Scholar
Scholar
7,170 Views
Registered: ‎02-27-2008

Re: mutiple clock frequencies in FPGA

selvam,

 

Read all about the DCM (or other clocking resources) in the appropriate user's guide to the part you are looking at.

 

For example, for Spartan 6:

 

http://www.xilinx.com/support/documentation/user_guides/ug382.pdf

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
Highlighted
Teacher
Teacher
7,151 Views
Registered: ‎07-09-2009

Re: mutiple clock frequencies in FPGA

Hi

 

 

or the simple one if you want slower clocks of using a counter to divide the clock !

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
0 Kudos
Highlighted
Observer
Observer
7,145 Views
Registered: ‎11-11-2009

Re: mutiple clock frequencies in FPGA

Thanks for your reply..

 

Actually we are designing a tracking loop using system generator 9.2i, where we need to give 3 different clock frequencies in a same block.

 

please note :Our hardware board supports only xilinx 9.2i. :smileysad: Hope xilinx 10 have a option to choose multiple clock frequency ?

0 Kudos
Highlighted
Xilinx Employee
Xilinx Employee
7,141 Views
Registered: ‎11-28-2007

Re: mutiple clock frequencies in FPGA

You won't be able use to multiple unique clock frequencies in a single system generator design (i.e. design with just one "System Genertor" token). That's still the case in version 10 and 11.

 

I don't know how you implement this "tracking loop", can you share your block diagram? If it's just sampling rate change using down-sampling or up-sampling, that will be automatically handled by the System Generator with clock enable signals. If you have more complex clocking requirement, you will need to partition your design into several subsystems with 1 clock per subsystem, you then put all subsystems together with "Multiple Subsystem Generator" block.

Cheers,
Jim
0 Kudos
Highlighted
Observer
Observer
7,139 Views
Registered: ‎11-11-2009

Re: mutiple clock frequencies in FPGA

Hi Jim,

 

Yes you are right, we can not use two different sampling rate in a system generator model with having only one 'System Generator token'.

 

But under the 'Multiple System Generator' token we can use two asynchronous clocks in two different subsystems at same level of hiararchy having seperate 'System Generator token' respectively.

 

But if we compile and generate the bit sream, then eventually two different bit streams are generated. That may be due to there is no wrapping of two different asynchronous clocks at model design level. I just want to know the way by which I could be able to get only one bit stream as a result.

0 Kudos
Highlighted
Xilinx Employee
Xilinx Employee
7,118 Views
Registered: ‎11-28-2007

Re: mutiple clock frequencies in FPGA

You need to use "Multiple System Generator" (MSG) token to generate the netlist files and a top level wrapper first (see attached screenshot). You then either use the generated ISE project file to implement the design or write another wrapper to instantiate the MSG design.

 

 

Cheers,
Jim
ScreenHunter_027.gif
Highlighted
Observer
Observer
7,116 Views
Registered: ‎11-11-2009

Re: mutiple clock frequencies in FPGA

Jim,

 

In  "Multiple System Generator" token we are not having any option to select our Lyrtech SFF SDR board for compilation, like "System Generator" token.

 

We need to write a wrapper file by ourselves or we can get it automatically (If yes, how?) !

 

Thanks & regards

selvam

0 Kudos
Highlighted
Visitor
Visitor
7,045 Views
Registered: ‎08-21-2008

Re: mutiple clock frequencies in FPGA

Hi Jim,

Since you are using Lyrtech SFF SDR model based design, it doesn't support more than one clock domaine in your design. 

You can mimic multiple clocks by playing with the sampling time. Otherwise you will have to dig into a lower level (HDL) in order to get working with more than one clock in your xilinx system generator model.

Hope this is helpful and you can confirm that with Lyrtech's tech support.

jack

0 Kudos