11-11-2011 09:18 AM
HI Xilinx team,
I am using Vertex5-LM506. And I'm trying to implement "Digital TDM-FDM translator with multistage structure" which is telecommunication one. by Xilinx package on simulink [MATLAB],
In the paper, I need to implement filter
the following is the error thst I receive:
Illegal Period, This blocks attempts to set period that is a non-integer multiple of the system rate
Error occurred during "Block Configuration"
Let me describe what I did:
I have system generator with 66.667 MHz pulse and 1/8122 sampling period
I have Sine input that is 1000Hz and has sampling rate of 1/8192
The input unit has also 1/8192 sampling period
error ..... it mean that there is problem with my period, what time of setting I can do keep in original setting of sampling 1/8192 untouched and get the result?
my model in attached
thanks in advance
11-14-2011 08:18 AM
Please use the FIR Compiler block. I used the v6.3 block in your design and it ran without an error.
11-15-2011 09:05 AM
The period on the counter in the MAC FIR appears to be set incorrectly with respect to the rest of your system. Right click the MAC FIR and select look under mask.