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grottenolm84
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Registered: ‎05-26-2009

problem with non-memory-mapped input ports

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Hi everybody,

 

my next problem with sysgen:

 

I want to start a hardware-cosimulation with my Xilinx Spartan 3e Starter Kit.

 

Evertime I try to generate the library with my non-memory-mapped input-ports I get the error message:

 

Illegal parameterization: location constraints

The number of pad locations must match the number of bits for the

output of this gateway.  The pad locations must be specified as a

cell array, e.g., {'MSB', ..., 'LSB'}.

 

Error in ==> xilinx_spartan_3e_starter_kit_libgen at 23

ss = add_input(lib, name, width, locs);

 

Error in ==> run at 57

          evalin('caller', [s ';']);

 

 

This only occurs with input ports -output ports can be generated by the s-function.

Perhaps anyone knows a solution for this....

 

thanks

 

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benchan
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Registered: ‎09-28-2007
Please try the attached script.

View solution in original post

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benchan
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Registered: ‎09-28-2007

There is a bug in the libgen script. To work around it, you can modify the script to put the line "set_param ( gcbh, 'LOC', locs );"  after "set_param( gcbh, 'width', width)".

grottenolm84
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Registered: ‎05-26-2009

I think I need some more help at that point.

 

Where can I find the "set_param( gcbh, 'width', width)"  in my generated libgen_script ?

There are only a lot of set_param(port... and set_param(ss.... lines in the script....

 

I have attached the generated libgen script

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benchan
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Registered: ‎09-28-2007
Please try the attached script.

View solution in original post

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grottenolm84
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Registered: ‎05-26-2009
Thank you very much ! Now the script runs perfectly.....
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