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Visitor
Visitor
12,034 Views
Registered: ‎11-05-2007

problems with implementation of a bit-stream on fpga

Hi @ all

I built a cotroll unit for a led segment. The simulation works fine and also the co-simulation. But when I implement the bit stream on the FPGA it dosen't work at all, nothing. I figured out when I only take the Input- and Output Gatway (Input the Button and Output the LED) it works. After I tryed that, I put only a delay with a latancy of one cycle between the gateway's and I got my bug back. I can push or not but the led don't care. The Led is allways on. I don't understand what is happened.

I use the xillinx sysgen 9.2, ISE 9.2i, and matlab 7.4

Thanks for your time


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Professor
Professor
12,032 Views
Registered: ‎08-14-2007

If you can make combinatorial logic work properly, but not sequential logic, that leaves the clock and reset.  Check pin assignments for clock and global reset.  If all else fails look at your design in the FPGA editor to see if you can find your flip-flop and where its clock and reset are coming from.

HTH,
Gabor
-- Gabor
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Visitor
Visitor
11,998 Views
Registered: ‎11-05-2007

thanks you are right the clock was the problem. But  now the timing is  much to fast.
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Explorer
Explorer
11,989 Views
Registered: ‎08-30-2007


Hello....

What do you mean the timing is too fast? If this means that the LED lights too quick for you to see then you can use a counter.
This counter will start counting when you push the button and will stop and reset when it will reach a limit. During this period an output
signal will constasntly be high (or low) and will drive the LED long enough for you to see (10ms will be sufficient so adjust the limit according to your clock)
When the counter stops the signal will switch the LED off.

If I understood incorrect and you mean something else then just ignore this message and give more info.

Hope that helps....

George

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Visitor
Visitor
11,976 Views
Registered: ‎11-05-2007

yes you can see it on the led.They should work with 1Hz but they do somthing in the area about 3kHz(I don't have a oscilloscopes at my place and I still try to get the chipScope running proper :-) ).
I use a accu, it gets loaded from a button (boolean) over a gateway that works on 1 Hz. after the accu i have a small logic that restets the accu. so i got a switch that switches between 1 and 0 (boolean), when I push the button. I needed a variable that can change between 1 and 0. The result goes to the led. In the simulation and the co-simulation it worked fine. So now I know  I have a timing problem but I can't find it.
In the System Generator Token you have to choose a targetable device:
Virtex2P(family)->xc2vp30(part name)->-7(speed)->ff896(package type) thats what I choosed there.
But I don't have the ff896 I have a ffg896 do you think that could cause my problems?

My settings on the token are:

Compilation:                                  Bitstream
Part:                                               Virtex2P xc2vp30 -7 ff896
Target directory:                             C:/DA/work/test
Synthesis tool:                               XTS
Hardware description language:   VHDL
FPGA clock period (in ns):            10         (If I want to have a slower rate I just change it for example to 20 (ns) and my FPGA works with 50Mhz?)(I think that dosent work in my case)
Clock pin location:                          AJ15    (pin from the SYSTEM_CLOCK)

And after the programm generated me the bit stream I use ISE iMPACT to drag it on the FPGA.

I have also a nother problem. I use the Audio Design with v8.2 System Generator for DSP (you can download it on the xilinx page (http://www.xilinx.com/univ/xupv2p.html)) as a base for my project. I needed the ac97 codec and it worked. But now I want to implement my controll unit and it dosent work. The same one we talked above. I got the impression that when i put some new gatways in the Xiliinx model they don't get implementet and dosen't appear in the bit stream. do you think this is this possible? Do I have to instantiate the gateways in the BSP (Board Support Package) in the yourboard.ucf? I did this too but it dosen't work neither(but i wasen't sure about the syntax). So I have no idea how i can implement some simple buttons and led.
Maybe there is some problem with the v8.2SysGen. I use a newer one the 9.2. But the codec works.


Thanks for your time I really appreciate


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Professor
Professor
11,967 Views
Registered: ‎08-14-2007

The FFG896 package option only differs from the FF896 in the composition of the solder balls, so that shouldn't affect your operation unless the part isn't properly soldered to the board.

If I'm not mistaken, the FPGA clock period should match the actual clock of your system.  So if the oscillator on your board runs at 50 MHz you should use 20 nS.  Changing the value won't actually change the clock frequency.  If your actual clock is 100 MHz, but you set the value to 20 nS (50 MHz) I would actually expect your design speed to double, if the system generator is providing the divisor for your 1 Hz clock.
-- Gabor
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Visitor
Visitor
11,956 Views
Registered: ‎11-05-2007

Ok thanks

Good to know that the G in FFG896 isn't a problem. I wasen't sure about that.
The System_Clock has the port AJ15 and it is a 100Mhz clk (10ns).
So I think the settings in the SysGen Token are ok. There has to be a other bug.

But when I put a sample period in the gatway it should implement this period. So it should sample with 1 Hz in this case, right?


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Visitor
Visitor
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Registered: ‎11-05-2007

I use the Audio Design with v8.2 System Generator for DSP (you can download it on the xilinx page (http://www.xilinx.com/univ/xupv2p.html)) as a base for my project. I needed the ac97 codec and it worked. After I had checked the function of the codec I wanted to use a button and a led in the model.
1.Step
Define and initialization of the constraints over Gatway, with the "Specify IOB location constraints" - field
I can compile the model and I get the bitstream. I checked also the ucf-file, what get generate from the SystemGenerator, during generation and I could see the right entries.
I draged the bitstream on the FPGA but the butten dosen't work.
2.Step
Define and initialization of the constraints over BSP (Board Support Package) (yourboard.ucf) in this case the file is called xupv2pro_wrapper.ucf and it look like:

Net clk_in LOC="AJ15";
Net clk_in IOSTANDARD = LVCMOS25;
Net clk_in PERIOD = 10000 ps;

Net reset_in LOC="AG5";
Net reset_in IOSTANDARD = LVTTL;
Net reset_in TIG;

NET AC97Clk PERIOD = 81.38 ns;
NET "AC97Clk" TNM_NET = "ac97bitclk_grp";

### AC97 Signals ###
NET AC97Clk       LOC = "F8";
NET AC97Reset_n   LOC = "E6";
NET Sync          LOC = "F7";
NET SData_Out     LOC = "E8";
NET SData_In      LOC = "E9";

NET AC97Clk       IOSTANDARD = LVTTL;
NET AC97Reset_n   IOSTANDARD = LVTTL;
NET Sync          IOSTANDARD = LVTTL;
NET SData_Out     IOSTANDARD = LVTTL;
NET SData_In      IOSTANDARD = LVTTL;

NET AC97Reset_n   DRIVE = 8 | SLEW = SLOW;
NET Sync          DRIVE = 8 | SLEW = SLOW;
NET SData_Out     DRIVE = 8 | SLEW = SLOW;


# Global period constraint
#NET "clk" TNM_NET = "clk_7f1f9c47";
#TIMESPEC "TS_clk_7f1f9c47" = PERIOD "clk_7f1f9c47" 40.0 ns HIGH 50 %;

# ce_4_7f1f9c47_group and inner group constraint
#Net "*ce_4_sg*" TNM_NET = "ce_4_152dfcd7_group";
#TIMESPEC "TS_ce_4_152dfcd7_group_to_ce_4_152dfcd7_group" = FROM "ce_4_152dfcd7_group" TO "ce_4_152dfcd7_group" 20833.33 ns;

###############################################################
######TEST/TEST/TEST/TEST/TEST/TEST/TEST/TEST##################
###############################################################

#LED

NET l3net LOC = "AA5";               #That are the LED's and the button's I would like to use
NET l2net LOC = "AA6";               #My first thought was that the name behind the NET is
NET l1net LOC = "AC3";              #the name I have to give the gareway in the model and than it would work
NET l0net LOC = "AC4";              #???

#Button

NET anet LOC = "AH4";
NET bnet LOC = "AH2";
NET cnet LOC = "AH1";

When I try to generate the model I get an error, how looks like:

Applying constraints in "xupv2pro_wrapper.ucf" to the design...

ERROR:NgdBuild:755 - "xupv2pro_wrapper.ucf" Line 44: Could not find net(s)

   'l3net' in the design.  To suppress this error specify the correct net name

   or remove the constraint.  The 'Allow Unmatched LOC Constraints' ISE property

   can also be set ( -aul switch for command line users).

ERROR:NgdBuild:755 - "xupv2pro_wrapper.ucf" Line 45: Could not find net(s)

   'l2net' in the design.  To suppress this error specify the correct net name

   or remove the constraint.  The 'Allow Unmatched LOC Constraints' ISE property

   can also be set ( -aul switch for command line users).

ERROR:NgdBuild:755 - "xupv2pro_wrapper.ucf" Line 46: Could not find net(s)

   'l1net' in the design.  To suppress this error specify the correct net name

   or remove the constraint.  The 'Allow Unmatched LOC Constraints' ISE property

   can also be set ( -aul switch for command line users).

ERROR:NgdBuild:755 - "xupv2pro_wrapper.ucf" Line 47: Could not find net(s)

   'l0net' in the design.  To suppress this error specify the correct net name

   or remove the constraint.  The 'Allow Unmatched LOC Constraints' ISE property

   can also be set ( -aul switch for command line users).

ERROR:NgdBuild:755 - "xupv2pro_wrapper.ucf" Line 51: Could not find net(s)

   'anet' in the design.  To suppress this error specify the correct net name or

   remove the constraint.  The 'Allow Unmatched LOC Constraints' ISE property

   can also be set ( -aul switch for command line users).

ERROR:NgdBuild:755 - "xupv2pro_wrapper.ucf" Line 52: Could not find net(s)

   'bnet' in the design.  To suppress this error specify the correct net name or

   remove the constraint.  The 'Allow Unmatched LOC Constraints' ISE property

   can also be set ( -aul switch for command line users).

ERROR:NgdBuild:755 - "xupv2pro_wrapper.ucf" Line 53: Could not find net(s)

   'cnet' in the design.  To suppress this error specify the correct net name or

   remove the constraint.  The 'Allow Unmatched LOC Constraints' ISE property

   can also be set ( -aul switch for command line users).

ERROR:Parsers:11 - Encountered unrecognized constraint while parsing.

ERROR:NgdBuild:19 - Errors found while parsing constraint file

   "xupv2pro_wrapper.ucf".



Writing NGDBUILD log file "xupv2pro_wrapper.bld"...

ERROR:Xflow - Program ngdbuild returned error code -1. Aborting flow

   execution...



Do you know why the button dosen't work in the first case? I think it has something to do with the translation of the wrapper-file .ngc and the netlist-file from the sysgen .ngc.
Do you know how I can get the conection between the gateway (button or LED) and the Pin-locatin-constraints?
I tryed to trace the way of the used gateways but i didn't found the link between them.

Thanks for your time
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