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gabiandpaulain7526
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Registered: ‎12-17-2017

sample period configuration (system generator)

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Hello, and thank you for your availability.


can someone please direct me in the setting of:
- FPGA clock period (10ns)
- simulink system period (sec)
- simple period
- specify explicit simple period
All documents or videos would be welcome.


 Thank you very much.

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balkris
Xilinx Employee
Xilinx Employee
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Registered: ‎08-01-2008

 

 

FPGA clock period(ns): Defines the period in nanoseconds of the system clock. The value need not be an integer. The period is passed to the Xilinx implementation tools through a constraints file, where it is used as the global PERIOD constraint. Multicycle paths are constrained to integer multiples of this value.

 

Clock pin location: Defines the pin location for the hardware clock. This information is passed to the Xilinx implementation tools through a constraints file. This option should not be specified if the System Generator design is to be included as part of a larger HDL design.

Provide clock enable clear pin: This instructs System Generator to provide a ce_clr port on the top-level clock wrapper. The ce_clr signal is used to reset the clock enable generation logic. Capability to reset clock enable generation logic allows designs to have dynamic control for specifying the beginning of data path sampling.

 

Simulink system period (sec): Defines the Simulink System Period, in units of seconds. The Simulink system period is the greatest common divisor of the sample periods that appear in the model. These sample periods are set explicitly in the block dialog boxes, inherited according to Simulink propagation rules, or implied by a hardware oversampling rate in blocks with this option. In the latter case, the implied sample time is in fact faster than the observable simulation sample time for the block in Simulink. In hardware, a block having an oversampling rate greater than one processes its inputs at a faster rate than the data. For example, a sequential multiplier block with an over-sampling rate of eight implies a (Simulink) sample period that is one eighth of the multiplier block’s actual sample time in Simulink. This parameter can be modified only in a master block.

Perform analysis: Specifies whether an analysis (timing or resource) will or will not be performed on the System Generator design when it is compiled. If None is selected, no timing analysis or resource analysis will be performed. If Post Synthesis is selected, the analysis will be performed after the design has been synthesized in the Vivado toolset. If Post Implementation is selected, the analysis will be performed after the design is implemented in the Vivado toolset.

 
Thanks and Regards
Balkrishan
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nagabhar
Xilinx Employee
Xilinx Employee
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Registered: ‎05-07-2015

HI @gabiandpaulain7526

Read chapter 3 for the system generator user guide in detail.
Especially the "timing and clocking" section in the page 31  of the Ug897
https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug897-vivado-sysgen-user.pdf

 

Thanks
Bharath
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balkris
Xilinx Employee
Xilinx Employee
2,414 Views
Registered: ‎08-01-2008

 

 

FPGA clock period(ns): Defines the period in nanoseconds of the system clock. The value need not be an integer. The period is passed to the Xilinx implementation tools through a constraints file, where it is used as the global PERIOD constraint. Multicycle paths are constrained to integer multiples of this value.

 

Clock pin location: Defines the pin location for the hardware clock. This information is passed to the Xilinx implementation tools through a constraints file. This option should not be specified if the System Generator design is to be included as part of a larger HDL design.

Provide clock enable clear pin: This instructs System Generator to provide a ce_clr port on the top-level clock wrapper. The ce_clr signal is used to reset the clock enable generation logic. Capability to reset clock enable generation logic allows designs to have dynamic control for specifying the beginning of data path sampling.

 

Simulink system period (sec): Defines the Simulink System Period, in units of seconds. The Simulink system period is the greatest common divisor of the sample periods that appear in the model. These sample periods are set explicitly in the block dialog boxes, inherited according to Simulink propagation rules, or implied by a hardware oversampling rate in blocks with this option. In the latter case, the implied sample time is in fact faster than the observable simulation sample time for the block in Simulink. In hardware, a block having an oversampling rate greater than one processes its inputs at a faster rate than the data. For example, a sequential multiplier block with an over-sampling rate of eight implies a (Simulink) sample period that is one eighth of the multiplier block’s actual sample time in Simulink. This parameter can be modified only in a master block.

Perform analysis: Specifies whether an analysis (timing or resource) will or will not be performed on the System Generator design when it is compiled. If None is selected, no timing analysis or resource analysis will be performed. If Post Synthesis is selected, the analysis will be performed after the design has been synthesized in the Vivado toolset. If Post Implementation is selected, the analysis will be performed after the design is implemented in the Vivado toolset.

 
Thanks and Regards
Balkrishan
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