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Anonymous
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setting for sysgen Explicit Period...

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What's the relation between these parameters..And how set them correctly?

1.Simulink system period

2.FPGA clock period

3.System Clock (Mhz)

4.Explicit Period

Just want to make 1Mhz sine wave:smileysad:

another question is that are these just affect in the simulation..Or implementation too!So if these parameters are important for the output result..I have to say that the documentation about dds and sysgen user guide are just bull**bleep**!!Because there is no good information about this problem...

Here is what I have done..So far:

 

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Xilinx Employee
Xilinx Employee
9,058 Views
Registered: ‎11-28-2007

Re: setting for sysgen Explicit Period...

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Yes as long as the input clock to your FPGA is 100MHz.

Cheers,
Jim

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Anonymous
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Re: setting for sysgen Explicit Period...

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by these parameterer:

fpga clock period =10 ns

simulink system period=10e-9

 

.......dds:

system clock =100Mhz

desired output=1Mhz

explicit sample period=0.00000001

 

and after more than 15min of simulation!!!! I got this:is that true?should it be take so long...am I right?:manmad:

 

DDS 1M.JPG
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Xilinx Employee
Xilinx Employee
8,208 Views
Registered: ‎11-28-2007

Re: setting for sysgen Explicit Period...

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Please take a look at this blog: http://myfpgablog.blogspot.com/2010/07/dds-in-system-generator-how-to-set-up.html to see if it helps.

 


@Anonymous wrote:

What's the relation between these parameters..And how set them correctly?

1.Simulink system period

2.FPGA clock period

3.System Clock (Mhz)

4.Explicit Period

Just want to make 1Mhz sine wave:smileysad:

another question is that are these just affect in the simulation..Or implementation too!So if these parameters are important for the output result..I have to say that the documentation about dds and sysgen user guide are just bull**bleep**!!Because there is no good information about this problem...

Here is what I have done..So far:

 


 

Cheers,
Jim
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Xilinx Employee
Xilinx Employee
8,204 Views
Registered: ‎11-28-2007

Re: setting for sysgen Explicit Period...

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When you run simulation, there is an one time initialization of DDS every time you change any parameter on the block. The initialization can take long time (sometimes painfully long). If you run simulation the 2nd time with the same parameters, it should be a lot faster.

 

Good news is that 12.2 (coming soon) has big improvement on the speed. I highly recommend you upgrade to 12.2 if possible once it's released.

 


@Anonymous wrote:

by these parameterer:

fpga clock period =10 ns

simulink system period=10e-9

 

.......dds:

system clock =100Mhz

desired output=1Mhz

explicit sample period=0.00000001

 

and after more than 15min of simulation!!!! I got this:is that true?should it be take so long...am I right?:manmad:

 


 

Cheers,
Jim
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Anonymous
Not applicable
8,192 Views

Re: setting for sysgen Explicit Period...

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thanks a lot abou the link and your response...

would you please tell me if these seeting are correct to implement on FPGA for making a 1Mhz sine wave ?

 

fpga clock period =10 ns

simulink system period=10e-9

.......dds:

system clock =100Mhz

desired output=1Mhz

explicit sample period=10e-9

 

are these parameters correct?

 

in your blog ,test 1 and test 2 are not real 1Mhz ? test 1 is:10mili Hz

test 2 is 100mili herz...

 

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Xilinx Employee
Xilinx Employee
8,176 Views
Registered: ‎11-28-2007

Re: setting for sysgen Explicit Period...

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Yes, your settings will get you a 1MHz sine wave.
Regarding results from test1 and test2: when you use simulink for digital signal processing, everything is sample based. You will find it a lot easier to think everything in terms of samples or clock ticks instead of MHz or any other time/frequency unit in Simulink. The absolute value you use for the simulink system period doesn't really matter. Once you choose a value, everything else will be scaled based on the simulink system period.
In test1, simulink system period is 1 (1Hz if you will)  = 100MHz in FPGA => 10miliHz in simulink = 10e-3*100e-6 = 1MHz
In test2, simulink system period is 0.1 (0.1Hz if you will)  = 100MHz in FPGA => 100miliHz in simulink = 100e-3*0.1*100e-6 = 1MHz


@Anonymous wrote:

thanks a lot abou the link and your response...

would you please tell me if these seeting are correct to implement on FPGA for making a 1Mhz sine wave ?

 

fpga clock period =10 ns

simulink system period=10e-9

.......dds:

system clock =100Mhz

desired output=1Mhz

explicit sample period=10e-9

 

are these parameters correct?

 

in your blog ,test 1 and test 2 are not real 1Mhz ? test 1 is:10mili Hz

test 2 is 100mili herz...

 


 

Cheers,
Jim
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Anonymous
Not applicable
8,121 Views

Re: setting for sysgen Explicit Period...

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Oh,tnx a lot for your response,

as my parameters takes very long to simulate..So for example if I use the test1 parameters,and then implement on Fpga,do I get real 1 Mhz sine wave?

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Xilinx Employee
Xilinx Employee
9,059 Views
Registered: ‎11-28-2007

Re: setting for sysgen Explicit Period...

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Yes as long as the input clock to your FPGA is 100MHz.

Cheers,
Jim

View solution in original post

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Anonymous
Not applicable
8,088 Views

Re: setting for sysgen Explicit Period...

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ooook,thank you very much:smileyhappy:

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Visitor
Visitor
7,273 Views
Registered: ‎09-08-2011

Re: setting for sysgen Explicit Period...

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Hi!
how schould i change this frequency to get another output frequency or more than one output frequency? for example iam trying to generate i thre signals 80, 85 and 90 MHZ.

i thank u for ur help
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