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Observer syrtic
Observer
351 Views
Registered: ‎03-04-2013

sysgen multiple clock domain

hello, I want to use multi clock domain in sysgen, and i make the following model:

src_domain: fpga period is 4ns, simulink period is 0.5s

dest_domain: fpga period is 8ns, simulink period is 1s

src_domain block generate 5 datas as fifo's din input, and its corresponding data_valid as fifo's we input.

dest_domain block receive data, but works at the half rate of src data. dest_domain block generate re signal by just invert fifo's empty output (without delay). and inside dest_domain block, the data_valid signal is just one cycle delay of re (corresponding to fifo's read latency).

the fifo's depth is 16, and i think the depth is enough to buffer the data, as in this demo only 5 data will be transmitted.

捕获1.PNG

but the simulation result puzzled me:

1) only data 1,3,5 have been received by dest_domain block, 2 and 4 are lost. i cannot figure out where is the problem.

2) fifo's output dcount gives the wrong number. as can be seen, when the empty goes high, which means no data in fifo, but dcount is still 1, means there is one data in fifo.

 

捕获2.PNG

i test this demo on (win7-64)+(vivado2017.3)+(matlab2017b).

and I also test this demo on (win7-64)+(vivado2018.1)+(matlab2018a).

the attached file is the simulink model tested on (win7-64)+(vivado2018.1)+(matlab2018a).

can anyone help me. thanks.

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1 Reply
Xilinx Employee
Xilinx Employee
125 Views
Registered: ‎12-14-2017

Re: sysgen multiple clock domain

Hi,

This is known issue which we are working on with the fifo block for multi clock designs. Please use DPRAM sysgen block instead of FIFO for multiclock designs for now.

Hope this unblocks you.

Regards,

Raju A.