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Observer
Observer
8,331 Views
Registered: ‎07-16-2008

sysgen raises standard exception: XNetlistEngine

When trying to generate a netlist from a model containing FIR Compiler v3_1 blocks the following error log is produced:

 

--------------------------------- Version Log ----------------------------------

Version Path

System Generator 10.1.2.1250 C:/Xilinx/10/DSP_Tools/common/bin/../../sysgen

AccelDSP 10.1.2.1250 C:/Xilinx/10/DSP_Tools/common/bin/../../AccelDSP

Matlab 7.6.0.324 (R2008a) C:/Programs/MATLAB/R2008a

ISE 10.1.02i C:/Xilinx/10/ISE

--------------------------------------------------------------------------------

Summary of Errors:

Error 0001: caught standard exception

Block: Unspecified

--------------------------------------------------------------------------------

 

Error 0001:

 

Reported by:

Unspecified

 

Details:

standard exception: XNetlistEngine:

An exception was raised:

com.xilinx.sysgen.netlist.NetlistInternal: couldn't run

"C:/Xilinx/10/ISE/bin/nt/coregen.exe -b makeproj 1>C:/Documents

and Settings/dh/My

Documents/projects/DBM/Matlab/Models/netlist/sysgen/coregen_xsoS/coregen_tmp/first_pass_coregen.txt

2>&1" at C:\Documents and Settings\dh\My

Documents\projects\DBM\Matlab\Models\netlist\sysgen\masterScript2541.pl

line 753

 

--------------------------------------------------------------------------------

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6 Replies
Newbie
Newbie
8,140 Views
Registered: ‎12-03-2008

I have a similar problem. Anyone already solve it?

 

 

Please help!

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Moderator
Moderator
8,137 Views
Registered: ‎08-01-2007

 

This error message tells us there may be some problems with CorCore Generator integrated within ISE as coregen.exe can not run. Can you try to open Core Generator standalone and check if it is able to generate FIR core. If it can not, this indicates CoreGenerator is corrupted. You have to reinstall ISE.

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Visitor
Visitor
7,056 Views
Registered: ‎06-24-2009

I believe this is a System Generator bug.  I am targeting a Virtex2 Pro with speed grade -6. 

Looking at the text in the Coregen project file that is generated, it has the following line,

   SET speedgrade = -7. 

 

This is an invalid speed grade.

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Contributor
Contributor
6,687 Views
Registered: ‎04-14-2009

I had the same problem and here is the link for the solution : http://forums.xilinx.com/xlnx/board/message?board.id=DSPTOOL&thread.id=1327

 

-- Walid F. Abdelfatah 

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Visitor
Visitor
6,649 Views
Registered: ‎06-24-2009

I have had issues in the past with long file names and spaces, so I reinstalled ISE from the "10.1" folder to one named "10_1", but still have the same problem with Sysgen and FIR Compiler 4.  I have no problem when targeting a Virtex 5 though, and noticed the part is correctly listed in the generated .CGP file.

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Explorer
Explorer
6,618 Views
Registered: ‎08-14-2007

I have seen similar problem when using Mult with Spartan-3/A device.Can you try generating FIR Compiler with DA option?

 

If you can generate FIR Compiler from Coregen, you can add it as a black box into Sysgen to work around the problem. You'd better let Xilinx notice this issue.

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