08-19-2015 03:34 PM
Connecting a Gateway in to a Gateway out, driving with a sine source and connecting scope sink. Simulating results in nothing displayed on the scope. Connecting a scope directly to the scope shows a sine wave. Basically all the Xilinx block sets 'don't work'. Matlab installed on drive c, vivado on drive d. Both eval licenses. All the block sets show up in Simulink and I get no warnings/errors.
08-19-2015 04:33 PM
What are your settings for gateway in and gateway out?
08-19-2015 04:42 PM
Gateway In - fixed-point signed(2's comp), 16bit, binary point14, round (unbiased)), overflow: satuate, no interface, no timing contraint.
Gateway Out - uncheck propate data type to output, translate into output port checked and set to 1 row and 1 column, no interface, no timing constraint.
this 'test' was taken from a subset of UG948 lab 2, where the simulink blocks behave correctly but the xilinx block set doesn't (step 2 in the lab). Figured I'd cut out everything except the gateways just to see if anything works and it appears not.
08-19-2015 04:45 PM
Okay, good information there. I'll check back tomorrow and see if it isn't answered. I have to go, sorry.
08-19-2015 04:55 PM
08-19-2015 05:03 PM
this is the case you are working on for me brian..thought I'd look on the forums and post this to see if others had ideas.2014.4 and matlab/simulink R2014b on win7 64-bit system. again, running through the tutorial ug948 lab 2 falls and that tutorial states to leave everything as defaults.
05-05-2018 10:58 PM
It is the 'Gateway Out' block which causes this kind of problem. If you check the model's sample time (Simulink menu "Display"->"Sample Time"->"All"), it shows clearly the 'Gateway Out' block outputs at a half rate of other blocks. That is, what you see is a down-sampled version of what you want to see.
I have no idea if this behavior of 'Gateway Out' is configurable by users.