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Contributor
Contributor
6,415 Views
Registered: ‎08-19-2015

system generator and matlab simulink problem

Connecting a Gateway in to a Gateway out, driving with a sine source and connecting scope sink.  Simulating results in nothing displayed on the scope.  Connecting a scope directly to the scope shows a sine wave.  Basically all the Xilinx block sets 'don't work'.  Matlab installed on drive c, vivado on drive d.  Both eval licenses.  All the block sets show up in Simulink and I get no warnings/errors.

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Voyager
Voyager
6,401 Views
Registered: ‎04-21-2014

Re: system generator and matlab simulink problem

What are your settings for gateway in and gateway out?

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Contributor
Contributor
6,398 Views
Registered: ‎08-19-2015

Re: system generator and matlab simulink problem

Gateway In - fixed-point signed(2's comp), 16bit, binary point14, round (unbiased)), overflow: satuate, no interface, no timing contraint.

 

Gateway Out - uncheck propate data type to output, translate into output port checked and set to 1 row and 1 column, no interface, no timing constraint.

 

this 'test' was taken from a subset of UG948 lab 2, where the simulink blocks behave correctly but the xilinx block set doesn't (step 2 in the lab).  Figured I'd cut out everything except the gateways just to see if anything works and it appears not.

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Voyager
Voyager
6,394 Views
Registered: ‎04-21-2014

Re: system generator and matlab simulink problem

Okay, good information there.  I'll check back tomorrow and see if it isn't answered.  I have to go, sorry.

***Many of us who help you are just FPGA enthusiasts, and not Xilinx employees. If you receive help, and give kudos (star), you're likely to continue receiving help in the future. If you get a solution, please mark it as a solution.***
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Xilinx Employee
Xilinx Employee
6,390 Views
Registered: ‎08-02-2011

Re: system generator and matlab simulink problem

This post is a bit ambiguous. Can you post more details about what the design looks like?

Also, simulink defaults to simulation time of 10. Depending on simulink system period and gateway sample period settings, this might be insufficient.

Also, make sure you do some searching of the forums. This type of thing is covered a lot on these forums.
www.xilinx.com
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Contributor
Contributor
6,381 Views
Registered: ‎08-19-2015

Re: system generator and matlab simulink problem

this is the case you are working on for me brian..thought I'd look on the forums and post this to see if others had ideas.2014.4 and matlab/simulink R2014b on win7 64-bit system.  again, running through the tutorial ug948 lab 2 falls and that tutorial states to leave everything as defaults.

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Newbie
Newbie
859 Views
Registered: ‎05-05-2018

Re: system generator and matlab simulink problem

It is the 'Gateway Out' block which causes this kind of problem. If you check the model's sample time (Simulink menu "Display"->"Sample Time"->"All"), it shows clearly the 'Gateway Out' block outputs at a half rate of other blocks. That is, what you see is a down-sampled version of what you want to see.

 

I have no idea if this behavior of 'Gateway Out' is configurable by users.

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