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Newbie
Newbie
9,618 Views
Registered: ‎05-17-2009

system generator error!

when i double click system generator in simulink ,it's display in follow:

 

 

 

--------------------------------- Version Log ----------------------------------
Version                                 Path
System Generator 10.1.3.1386            D:/Xilinx/10.1/DSP_Tools/common/bin/../../sysgen
AccelDSP 10.1.3.1386                    D:/Xilinx/10.1/DSP_Tools/AccelDSP
Matlab 7.6.0.324 (R2008a)               D:/MATLAB/R2008a
ISE 10.1.03i                            d:/Xilinx/10.1/ISE
--------------------------------------------------------------------------------
Summary of Errors:
Error 0001: Undriven input port
     Block: 'xlsysgen_one_block_sim/Reg Out1'
--------------------------------------------------------------------------------

Error 0001:

Reported by:
  'xlsysgen_one_block_sim/Reg Out1'

Details:
The input ports on this block must be driven by other Xilinx blocks
--------------------------------------------------------------------------------

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15 Replies
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Voyager
Voyager
9,614 Views
Registered: ‎05-09-2008

Please send snapshot of model.

 

Kappa.

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Contributor
Contributor
9,603 Views
Registered: ‎05-22-2008

hi

looks line u have an undriven input port..

maybe u haven't connected a gateway in block at input.

 

sandeep

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Newbie
Newbie
9,592 Views
Registered: ‎05-17-2009

the snapshot in the attachment!
12.bmp
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Highlighted
Contributor
Contributor
9,571 Views
Registered: ‎05-22-2008

it seems there is a problem with ur Mcode block, it  does not has input and output ports.

it must be a programe error

 

sandeep

 

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Newbie
Newbie
9,556 Views
Registered: ‎05-17-2009

this is not my mcode. this is mcode of system generator. when i double click the system gererator icon in the simulink library brower,then above error is show.
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Visitor
Visitor
7,390 Views
Registered: ‎02-16-2011

Hello,

how to overcome this problem?

I am not able to rectify this error.

can you please help me  in this.

 

Regards

Anurag

attach_1.JPG
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Contributor
Contributor
7,385 Views
Registered: ‎05-22-2008

Hi Raguna

 

u have connected only one input to AddSub block. The undrived input of this block is causing this error. If u do not reuire this block u should remove it.

 

cheers

sandeep

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Visitor
Visitor
7,380 Views
Registered: ‎02-16-2011

Thankyou for the quick reply.

Even after giving inputs, I am facing the same problem.

 

 

Regards

Raguna

attach_2.JPG
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Highlighted
Contributor
Contributor
7,366 Views
Registered: ‎05-22-2008

hi

 

this time simulation failed as u have connected the o/p of mux to input of previous one.

do try to read the error message, it will give u a hint .

 

cheers

sandeep

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Visitor
Visitor
4,626 Views
Registered: ‎02-16-2011

Thankyou.

I could rectify this.

but the simulation is very fast that i can not figure out the results properly.

 

PS:PLease find attachment of the simulink file.

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Moderator
Moderator
4,610 Views
Registered: ‎08-01-2007

 
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Moderator
Moderator
4,610 Views
Registered: ‎08-01-2007

 

 

There is a feedback path in the model, try to add "assert" block into this model.

 

 

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Newbie
Newbie
4,433 Views
Registered: ‎10-30-2011

hi every one

i have problem with this block set

in its data sheet has been said that when "fwd_inv" not been driven its high

but when i dont drive it or even drive it with high or low logic in any condition it give error that its not driven

can anybody help me ?

model file has been attached

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Xilinx Employee
Xilinx Employee
4,421 Views
Registered: ‎02-11-2010

Is this the same issue seen in this thread, if so, please provide the error message you are seeing, if not, please start a new thread.
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Xilinx Employee
Xilinx Employee
4,419 Views
Registered: ‎02-11-2010

My previous message is for rafael1986
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