cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Behrouz
Visitor
Visitor
557 Views
Registered: ‎03-09-2021

system generator failure during build process

Hello,

I am facing an error during build process. It seems that the build process is failing due to long path names. Following is the error

 

E10.png

 

I reduced the model name size to be one character which is "A" and its folder name to have three characters. Therefore the model patch is "C:\LTE\A". The model is the same model which I used to build and I did not change any subsystem name and I did not add any subsystem. 
I don't understand the reason for this error. Model path is pretty short and the model is the same as I used to build.
Do you have any idea about the solution for this problem? I am attaching Vivado log file to this post.

I would appreciate it if you let me know your opinion as soon as possible.

Thank you in advance.

 

0 Kudos
9 Replies
vkanchan
Xilinx Employee
Xilinx Employee
475 Views
Registered: ‎09-18-2018

Hi @Behrouz ,

It appears that you have blocks in your model which have long names. A block may resolve into an IP and its directory name will be same at that of the block's

Please reduce the block/subsystem names in your design and retry.

 

0 Kudos
Behrouz
Visitor
Visitor
459 Views
Registered: ‎03-09-2021

I could compile the same model last week. I did not add any block or subsystem to the model to increase block/subsystem path. How can this happen? It should have a reason other than the model subsystems because the model is the same model and Xilinx was able to compile the same model before. 

0 Kudos
Behrouz
Visitor
Visitor
337 Views
Registered: ‎03-09-2021

Would you please help me to find the reason for this error. I reduced the model path to "C:\LTE\A4" which is pretty short path. I also deleted almost all blocks in my model and reduced it to very very simple model. I am attaching the model and its screen shots to this post.

Complete Model Overview:

Model overview.png

 FPGA Model Overview:

FPGA model overview.png

I am still facing with the same error. It says:

Implementation of the results of the Xilinx System Generator build failed. Some cores could not be compiled by Xilinx Coregen due to too long paths.

Coregen cannot handle long directory names. Choose a shorter path and/or shorter subsystemnames.

Error Message.png

I believe there is another reason for this issue because the model path is very short and model does not have any subsystem.Please let me know your thoughts and solution for this problem as soon as possible.

Thank you in advance. 

FPGA model overview.png
Error Message.png
Model overview.png
0 Kudos
vkanchan
Xilinx Employee
Xilinx Employee
309 Views
Registered: ‎09-18-2018

Hi @Behrouz ,

At which step are you facing the issue ? Is it during the code generation ? If so, what is the compilation target i.e. HDL netlist, IP cataog, or dcp  ? 

Does the simulation work fine ?

Is there any other software running here like dSPACE software which invokes the build  or is it only Sysgen that is used here ?

One simple step is to delete the cache path (path can be found using the "xilinx.environment.getcachepath" command on the MATLAB console) and target the code generation to a different folder.

 

0 Kudos
Behrouz
Visitor
Visitor
288 Views
Registered: ‎03-09-2021

Hi Vkanchan,

This error happens at FPGA build process and compilation target is HDL netlist. Following image shows more information about system generator status:

Behrouz_0-1622133539536.png

 

I can work with Simulink and develop the model without any issue. 


I have dSPACE 2015 software installed on my computer. Following is detailed information about the installed dSPACE packages. 
========================================================================================
Configuring dSPACE(R) Software for MATLAB(R) 8.5.0.197613 (R2015a) ...

RTI Real-Time Interface to Simulink (RTI1401) 7.5p3 
RTICAN RTI CAN Blockset 3.4.1p4
RTIRPCU RTI RPCU Blockset 2.2.1 
RTIFPGA RTI FPGA Programming Blockset 3.0.2 
DSMPBLIB Model Port Block Library 3.1
DSRT dSPACE Run-Time Target (DSRT) 3.1p2
DSMSBLIB Model Separation Block Library 3.1p1
RTIUSBFlightRec RTI USB Flight Recorder Blockset 1.2 
DSMLCON24 dSPACE MATLAB Connection 2.4 (win64) 2.4 
========================================================================================

*** RTI Platform Support RTI1401 activated.

Build process is initiated by FPGA setup block and I don't think dSPACE to be involved with this process. Following picture shows parameters tab at FPGA setup block. 

Behrouz_1-1622134222769.png

I deleted the cache folder as you can see from following image. Unfortunately, I faced with the same error when I execute FPGA build.

Behrouz_0-1622135630963.png

 

Behrouz_1-1622135669885.png

 

Thanks in advance for your help. Looking forward to learn your suggestions.

Regards,
Behrouz

 

 

 

0 Kudos
Behrouz
Visitor
Visitor
221 Views
Registered: ‎03-09-2021

Hello Vkanchan,

Do you have any suggestions for me to solve this issue related to the Xilinx error? I would appreciate it if you let me know your idea as soon as you can.

Regards,
Behrouz

0 Kudos
Behrouz
Visitor
Visitor
182 Views
Registered: ‎03-09-2021

Hello Vkanchan,

I need Xilinx to help me to solve this issue. Would you please assist me with this problem as soon as possible? My project is halted due to this error from Xilinx code generation. Looking forward to receiving your ideas.

Regards,
Behrouz

 

0 Kudos
vkanchan
Xilinx Employee
Xilinx Employee
132 Views
Registered: ‎09-18-2018

Hi @Behrouz ,

The build process is triggered from dSPACE SW in this case. What is the result if the code generation is executed from the Sysgen token ? Does it complete successfully ?

I also suggest to report this to dSPACE as well to check if there is an issue from their SW which seems to be controlling the design here.

0 Kudos
Behrouz
Visitor
Visitor
84 Views
Registered: ‎03-09-2021

Hello Vkanchan,

our licence for the Xilinx software has expired couple of days ago and I am trying to renew the licence. I will try to build the code from Sysgen token when I received the new licence. I will let you know about code generation results.

Regards,
Behrouz Irdmousa

 

0 Kudos