03-25-2019 12:44 PM
I create some block on the system generator with some AXI4-lite read/write registers. in the original the system clock and AXI-Bus clock is 40MHz.
I want to increase only the AXI bus clock to 100MHz.
This registers can be updtae by the ZYNQ and by the subsystem in the IP, my questions how to syncronize these registers in the system generator?
How to connect the new clock in the VIVADO block diagram?
04-10-2019 09:20 AM
Below is what I understood,
You have certain SysGen design where the frequecy is set to 40 MHz (or some other) in sysgen token. Next, you generated the IP for this design and using it with znyq. Now, you want to use the IP at 100 MHz.
If above is the correct question, then all you need to do is "change the frequency in the constraint files in Vivado project". No changes are required in the SysGen design.
04-12-2019 07:37 AM
No it's not what i need, I have in the IP, AXI-lite register ( which created by using In-Gate and Out-gate) , I want to change ONLY the clock on the AXI-lite registers.
If i change the system clock, It will require to change almost each block which I have on the IP , (because I'm using constant with Relational).
I need multiple clock domain, one for the IP logic and faster clock for the AXI-Lite registers.
I tired to do the example on the Lab 4:
It's not a good solution for my design.
04-19-2019 10:49 AM - edited 04-19-2019 10:50 AM