08-28-2019 01:14 AM
I have built very large DSP project using System Generator v3.1 in 2005.
There was only one problem in the workflow that time - I needed to implement DLL clock manager "by hand" every time I had some change made in the project.
I saw that there is some DCM support in later versions of System Generator but do not see it in latest System Generator`s docs.
What is right way to implement DCM in System Generator`s project right now?
I am asking becouse I need to make decision to migrate my project to the latest System Generator version or not.
Sorry for my naive question, but I am working with FPGA only time to time, not averyday.
09-04-2019 03:40 AM
Dear Xilinx employees,
Was my question to much complex or too much simple I do not understand but anyway,
please advise, what is the most time saving way to implement DCM in the project created by System Generator!
09-04-2019 10:35 PM
I have couple of queries before answering your question.
Support of DCM means, what is its significance in the design ?
you want to specify clock frequency with which algorithm runs in the FPGA ? or
You want to create machanism to run some portion of the design at one rate and other portion of the design at other rate ?
09-05-2019 03:32 AM
Thank you for question, Raju,
It is the simplest case. The project on FPGA needs just one 8 x 24.576=196.608 MHz clock.
The available clock source is 24.576 MHz. The DCM must multiply 8 times.
09-05-2019 03:47 AM
Thanks for writing to us!!
ISE version of sysgen had the support of DCM but Vivado version of sysgen does not have it. The idea here is to have a portion of the design from sysgen, create an IP and stitch it to the bigger design in the vivado
As there is no support of DCM implementation in vivado version of sysgen, The only way to specify FPGA clock period in sysgen is to open the sysgen token and set the FPGA clock period directly. We can not do frequency multiplication in sysgen, that should be done in Vivado.
Hope it helps.
09-06-2019 05:03 AM
Thank you for opinion,
This is ruining all the beauty of the System Generator.
All ports (62 in my case) must be added manually to the IP block (ok, maybe by use of tcl script) but anyway, lot of manual work.
How about adding the "Clocking Wizard" block to the set of System Generator's blocks?
The "Black Box" option looks like is not working for the clock management ...
09-12-2019 10:34 PM
Here the idea to make sysgen usage easier to the users. SYsgen users do not need to worry about clocking and control signals, just need to use the data paths ( most of the cases ) to validate the algorithm or the design. Once everything looks fine then we generate IP/RTL for the sysgen design and stitch it to IPI design in the vivado. This is where we can use clock wizard, DCM etc
Hope this helps.