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tatchakorn
Contributor
Contributor
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Registered: ‎08-12-2013

time domain zero padding

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Hello, how can i release time domain zero-padding in SysGen ?

for example,  i have 64 samples and i need to pad it with zeros.

ty

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bwiec
Xilinx Employee
Xilinx Employee
12,606 Views
Registered: ‎08-02-2011

Imagine that you are getting a new sample coming in every clock cycle. When you receive 64 samples, you need to switch to a signal driven by gnd for N more samples (depending on how many zeros you need).

 

So you would need:

- The ability to count to 64+N

- Ability to compare the count value to the value of 64

- A circuit component that would allow you to switch between two signal sources

 

www.xilinx.com

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bwiec
Xilinx Employee
Xilinx Employee
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Registered: ‎08-02-2011

What do you think you should do? If you have a signal and you want to insert zeros at the end of a signal, what would you need?

www.xilinx.com
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tatchakorn
Contributor
Contributor
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Registered: ‎08-12-2013

idk :(

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bwiec
Xilinx Employee
Xilinx Employee
12,607 Views
Registered: ‎08-02-2011

Imagine that you are getting a new sample coming in every clock cycle. When you receive 64 samples, you need to switch to a signal driven by gnd for N more samples (depending on how many zeros you need).

 

So you would need:

- The ability to count to 64+N

- Ability to compare the count value to the value of 64

- A circuit component that would allow you to switch between two signal sources

 

www.xilinx.com

View solution in original post

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tatchakorn
Contributor
Contributor
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Registered: ‎08-12-2013

Am I right to understand you?

ezl64.jpg
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bwiec
Xilinx Employee
Xilinx Employee
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Registered: ‎08-02-2011
Looks like you're on the right path! There may be a few little things to work out so you should start running some simulations and go from there.
www.xilinx.com
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tatchakorn
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Contributor
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Registered: ‎08-12-2013

Thank you very much,

but i have some problems: 

i start running some simulations and obtained the different results from simulink and sysgen's padding. How can i fix that?

 

 

 

s398.jpg
o2fo.jpg
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eilert
Teacher
Teacher
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Registered: ‎08-14-2007

Hi,

that's probably due to the buffer and unbuffer blocks which cause some extra initial latency in the simulink path.

 

While the behavior looks similar there might be differences in the sampling between the two approaches too.

 

The tools do exactly what you tell them to do.

But are you able to tell the tools exactly what you want them to do?

That's the big challenge we all have to face every day. :-)

 

So don't be disappointed. Every little detail can change the behavior of some circuit and trying to describe the same behavior in two different ways (Simulink vs. Xilinx blockset) is not easy and sometimes actually very tricky.

 

Have a nice simulation

  Eilert

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tatchakorn
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Registered: ‎08-12-2013

Ofc, i understand that :) 

I'm trying to implement a simulink model in sysgen.

ty

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tatchakorn
Contributor
Contributor
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Registered: ‎08-12-2013

Any ideas?

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tatchakorn
Contributor
Contributor
4,799 Views
Registered: ‎08-12-2013

Hello again.

I solved the problem - using the Dual Port RAM with sample time N on port A, and sample time 2N (or other) on port B.

Data comes into dual port ram, then out from port B and then to multiplexer with data\zeros.

Thanks all.

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