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Observer
Observer
10,146 Views
Registered: ‎09-04-2007

timing constraint error : hardware co-sim with spartan 3A DSP starter board

Hi,
I intended to use hardware co-simulation feature of System Generator for my design. I am using Spartan 3A DSP starter kit, so I installed the board according to http://www.xilinx.com/products/boards/s3estarter/files/s3esk_sysgen_hw_in_loop.pdf
with spartan 3ADSP 1800 FPGA, speed grade 4, and on board clock souce of 125MHz.

I used an 12bit adder from xilinx block set in order to familiarize with the procedures, but I always get error when I tried to generate hardware co-sim block.

------------------------------------------------------------------------------------------------------

Constraint | Check | Worst Case | Best Case | Timing | Timing

| | Slack | Achievable | Errors | Score

------------------------------------------------------------------------------------------------------

* NET "ibufg_comp_O" PERIOD = 8 ns HIGH 50% | SETUP | -1.508ns| 9.508ns| 27| 14245

| HOLD | 0.900ns| | 0| 0

------------------------------------------------------------------------------------------------------


Does this mean I cannot even run a simple adder on the FPGA at 125MHz? What can I do to solve this problem?

Thanks in advance!

zy
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Xilinx Employee
Xilinx Employee
10,142 Views
Registered: ‎08-07-2007

The AddSub block in the Xilinx Blockset has a Latency field that is set to 0 by default.  This means your input data must get from the input register through the full 12 bit adder to the output register in one clock cycle.  Increasing the latency through this block will add pipelining registers and will allow it to run at a higher clock rate.
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Observer
Observer
10,125 Views
Registered: ‎09-04-2007

Hi,

I am aware of the option of changing number of pipeline stages. But the system I am designing has to use a 4 input 12 bit adder, which means I need the result from 3 12bit adders within one clock cycle.

Since a single 12 bit adder already fails timing constraint, does this mean my system will never work?

And in my system controller I will be using a lot of address counters and large comparators (up to 24 bit) for the state machine to generate control signals, I now have the impression that my system is never going to run at 125MHz...

Please give me some advice!

Thanks,
zy


Message Edited by zhouyun on 01-09-2008 01:59 AM
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Observer
Observer
10,121 Views
Registered: ‎09-04-2007

Hi,

To provide some more information:

I am new to the design environment of sysgen and simulink, my previous design works are all based on standard ISE design flow.

I have a system ready, in this case, a 12bit adder, and if it could not run at 125 MHz, I can use DCM to reduce the clock frequency. The design was fine at lower speed (eg. 75MHz) and was able to be downloaded to the FPGA and operation was verified. To my understanding the same design should also work using sysgen.

Since the design fails at 125MHz, I imported the design using VHDL including DCM and a equivalent 12 bit adder. But I still have the same errors for timing constraints when I try to run hardware co-simulation.

My questions are:
1) Where do these timing constraints originated from? Since I did not specifiy and .ucf file for the design.
2) Is there any possiblity to change these constraints?
3) Since the design was imported into sysgen as black box, does this mean any change within the source code will not be seen by sysgen or the synthesis/PAR tool?
4) Any suggestions on getting around this problem?

Thanks again in advance!

zy

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Xilinx Employee
Xilinx Employee
10,113 Views
Registered: ‎08-07-2007

You can run the adder portion of your design at a lower rate by using downsample blocks prior to the Adder block.  You'll need to either pipeline your design further or run it at a lower rate if it is failing timing.
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