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salman866
Contributor
Contributor
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Registered: ‎11-26-2010

two dimentional fft

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hi,

I am a student and new user to system generator. I want to implement fftshift using system generator but

i don't find any block to do so. I am stuck. Please help me with this.

secondly i want to ask that if there is any possibility of implementing two dimensional fft in system genrator.

For example I have 8X8 matrix and i want to take fft first row wise and than i want to take column  wise.                                     

                                                                                                                     SALMAN

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eschei
Xilinx Employee
Xilinx Employee
9,342 Views
Registered: ‎02-09-2009

You need to build a 1/4 turn buffer between the 1D FFTs. If the 2D FFT is 8x8, then you should be able to build this using FPGA internal memory. The Dual-Port RAM would work well for this because you can write the output of the first FFT into RAM on port-A, then read out in a different order from port-B. You would need to build two different address generators for port-A and port-B. Using portA you would just write the results from each horizontal line serially into memory. Then from port-B you would read the data by skipping eight addresses every increment, effectively reading the vertical lines of the eight by eight matrix serially into the 2nd FFT.

 

For larger 2D FFTs at some point you would have to move to external memory because the entire matrix needs to be passed through the 1st FFT before the 2nd FFT can begin.

 

-es

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balkris
Xilinx Employee
Xilinx Employee
8,297 Views
Registered: ‎08-01-2008

 

Hi ,

 

 

 

Xilinx doesn't have any core for 2D FFT . However you can implement using 1D FFT.

 

 

 

For 8X8 FFT you need to calculate 8 point FFT for each row then transpose the result  again perform 8 point FFT for transpose data.

 

 

 

Make sure you are doing proper handshaking of signal

 

Thanks and Regards
Balkrishan
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salman866
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Registered: ‎11-26-2010

Actually the same thing was in my mind too but the problem was that the data in fpga has to be entered serially

which means that i cannot transmit the whole matrix simultaineously therefore i was confused how to combine this data in matrix form again after entering it serially within the fpga to take its transpose.

please reply if you have any solution to this problem.

 I have the simulink model of the same thing which i want to implement. I can send it to you if you are still not sure what i am talking about.

                            SALMAN 

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eschei
Xilinx Employee
Xilinx Employee
9,343 Views
Registered: ‎02-09-2009

You need to build a 1/4 turn buffer between the 1D FFTs. If the 2D FFT is 8x8, then you should be able to build this using FPGA internal memory. The Dual-Port RAM would work well for this because you can write the output of the first FFT into RAM on port-A, then read out in a different order from port-B. You would need to build two different address generators for port-A and port-B. Using portA you would just write the results from each horizontal line serially into memory. Then from port-B you would read the data by skipping eight addresses every increment, effectively reading the vertical lines of the eight by eight matrix serially into the 2nd FFT.

 

For larger 2D FFTs at some point you would have to move to external memory because the entire matrix needs to be passed through the 1st FFT before the 2nd FFT can begin.

 

-es

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francism
Xilinx Employee
Xilinx Employee
8,270 Views
Registered: ‎05-23-2008

Hi

As another hint visit our website and look for the product page for the FFT http://www.xilinx.com/products/ipcenter/FFT.htm

on there you will see a link for C-models. Get hold of the model for your version of the IP.

There is docuamtation that will show you how to use the model within matlab and you could write some matlab code to bring in your image, or what ever data it is, and then take it through the c-model. You could then compare that with 2d fft simulink model you have done or just write some matlab code.

 

Mike

salman866
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Contributor
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Registered: ‎11-26-2010

@ eschei

Thanks a lot for  a wonderfuill solution. That is really helpfull.

Actually I am using vertex 4. Can its internal memory be able to handle a 128x128 matrix. If not what is the maximum

that it can handle.

                               SALMAN

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balkris
Xilinx Employee
Xilinx Employee
8,244 Views
Registered: ‎08-01-2008

Memory size depends upon target you can check device datasheet for detail.

Thanks and Regards
Balkrishan
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