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Pitto
Observer
Observer
519 Views
Registered: ‎03-25-2020

ultra96v2のbitStreamがfailedになるエラーについて

ultra96v2ボードを以下のサイトの通りに構築しました。

しかしgenerate bitStreamで

"design_1_zynq_ultra〜synth_1 failed"

というエラーが上部に出てbitStreamが完了しません。

tcpコンソールやメッセージ、ログにはエラーは出てないです。

なぜultra96v2のボードでこのエラーがでるか、その解決策を教えていただけないでしょうか?

 

サイト

https://qiita.com/basaro_k/items/6841c99c39ff12851847

https://highlevel-synthesis.com/how-to-create-ultra96v2-linux-based-platform-in-xilinx-vitis-2019-2/

 

B3157689-3C53-428B-ADA4-44BC23A63CA5.png
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3 Replies
watari
Teacher
Teacher
469 Views
Registered: ‎06-16-2013

Hi @Pitto 

 

Would you share vivado.log or something like log file on your working directory ?

It's hard to investigate the route cause without detail information even if you show some links...

 

Best regards,

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Pitto
Observer
Observer
437 Views
Registered: ‎03-25-2020

This is log of ‘runme.log’ and 'vivado.log', and 'runme.log' path is (runme.logとvivado.logのファイル内容です。それとrunme.logのpathは下の通りです)

/home/<project_name>/ultra96base.runs/design_1_zynq_ultra_ps_e_0_0_synth_1/runme.log

This log will be related to failed bitstream, but do not know why this cause. Please tell me its solution.(runme.logの内容がbitstreamのエラーに関係してると思うのですが、原因がわかりません。解決策を教えてください。)

 

***The path’s files***

***The path’s files***

$ ls /home/<project_name>/ultra96base.runs/design_1_zynq_ultra_ps_e_0_0_synth_1

ISEWrap.js                                    htr.txt

ISEWrap.sh                                    rundef.js

__synthesis_is_running__                      runme.bat

design_1_zynq_ultra_ps_e_0_0.tcl              runme.log

design_1_zynq_ultra_ps_e_0_0.vds              runme.sh

design_1_zynq_ultra_ps_e_0_0_4814.backup.vds  vivado.jou

dont_touch.xdc                                vivado.pb

gen_run.xml                                   vivado_4814.backup.jou

 

runme.log

*** Running vivado

    with args -log design_1_zynq_ultra_ps_e_0_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source design_1_zynq_ultra_ps_e_0_0.tcl





****** Vivado v2019.2 (64-bit)

  **** SW Build 2708876 on Wed Nov  6 21:39:14 MST 2019

  **** IP Build 2700528 on Thu Nov  7 00:09:20 MST 2019

    ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.



source design_1_zynq_ultra_ps_e_0_0.tcl -notrace

create_project: Time (s): cpu = 00:00:03 ; elapsed = 00:00:11 . Memory (MB): peak = 1551.027 ; gain = 120.016 ; free physical = 79 ; free virtual = 312

Command: synth_design -top design_1_zynq_ultra_ps_e_0_0 -part xczu3eg-sbva484-1-e -mode out_of_context

Starting synth_design

Attempting to get a license for feature 'Synthesis' and/or device 'xczu3eg'

INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xczu3eg'

INFO: [Device 21-403] Loading part xczu3eg-sbva484-1-e



*** Running vivado

    with args -log design_1_zynq_ultra_ps_e_0_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source design_1_zynq_ultra_ps_e_0_0.tcl





****** Vivado v2019.2 (64-bit)

  **** SW Build 2708876 on Wed Nov  6 21:39:14 MST 2019

  **** IP Build 2700528 on Thu Nov  7 00:09:20 MST 2019

    ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.



source design_1_zynq_ultra_ps_e_0_0.tcl -notrace

create_project: Time (s): cpu = 00:00:03 ; elapsed = 00:00:14 . Memory (MB): peak = 1550.906 ; gain = 122.016 ; free physical = 74 ; free virtual = 1953

Command: synth_design -top design_1_zynq_ultra_ps_e_0_0 -part xczu3eg-sbva484-1-e -mode out_of_context

Starting synth_design

Attempting to get a license for feature 'Synthesis' and/or device 'xczu3eg'

INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xczu3eg'

INFO: [Device 21-403] Loading part xczu3eg-sbva484-1-e

INFO: Launching helper process for spawning children vivado processes

INFO: Helper process launched with PID 3332 

---------------------------------------------------------------------------------

Starting RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:37 . Memory (MB): peak = 2421.559 ; gain = 0.000 ; free physical = 65 ; free virtual = 1054

---------------------------------------------------------------------------------

INFO: [Synth 8-6157] synthesizing module 'design_1_zynq_ultra_ps_e_0_0' [/home/hagi/ultra96base/ultra96base.srcs/sources_1/bd/design_1/ip/design_1_zynq_ultra_ps_e_0_0/synth/design_1_zynq_ultra_ps_e_0_0.v:59]

INFO: [Synth 8-6157] synthesizing module 'zynq_ultra_ps_e_v3_3_1_zynq_ultra_ps_e' [/home/hagi/ultra96base/ultra96base.srcs/sources_1/bd/design_1/ip/design_1_zynq_ultra_ps_e_0_0/hdl/zynq_ultra_ps_e_v3_3_1.v:282]

Parameter C_MAXIGP0_DATA_WIDTH bound to: 128 - type: integer 

Parameter C_MAXIGP1_DATA_WIDTH bound to: 128 - type: integer 

Parameter C_MAXIGP2_DATA_WIDTH bound to: 32 - type: integer 

Parameter C_SAXIGP0_DATA_WIDTH bound to: 128 - type: integer 

Parameter C_SAXIGP1_DATA_WIDTH bound to: 128 - type: integer 

Parameter C_SAXIGP2_DATA_WIDTH bound to: 128 - type: integer 

Parameter C_SAXIGP3_DATA_WIDTH bound to: 128 - type: integer 

Parameter C_SAXIGP4_DATA_WIDTH bound to: 128 - type: integer 

Parameter C_SAXIGP5_DATA_WIDTH bound to: 128 - type: integer 

Parameter C_SAXIGP6_DATA_WIDTH bound to: 128 - type: integer 

Parameter C_SD0_INTERNAL_BUS_WIDTH bound to: 4 - type: integer 

Parameter C_SD1_INTERNAL_BUS_WIDTH bound to: 4 - type: integer 

Parameter C_PL_CLK0_BUF bound to: TRUE - type: string 

Parameter C_PL_CLK1_BUF bound to: FALSE - type: string 

Parameter C_PL_CLK2_BUF bound to: FALSE - type: string 

Parameter C_PL_CLK3_BUF bound to: FALSE - type: string 

Parameter C_NUM_F2P_0_INTR_INPUTS bound to: 1 - type: integer 

Parameter C_NUM_F2P_1_INTR_INPUTS bound to: 1 - type: integer 

Parameter C_NUM_FABRIC_RESETS bound to: 1 - type: integer 

Parameter C_EMIO_GPIO_WIDTH bound to: 1 - type: integer 

Parameter C_USE_DIFF_RW_CLK_GP0 bound to: 0 - type: integer 

Parameter C_USE_DIFF_RW_CLK_GP1 bound to: 0 - type: integer 

Parameter C_USE_DIFF_RW_CLK_GP2 bound to: 0 - type: integer 

Parameter C_USE_DIFF_RW_CLK_GP3 bound to: 0 - type: integer 

Parameter C_USE_DIFF_RW_CLK_GP4 bound to: 0 - type: integer 

Parameter C_USE_DIFF_RW_CLK_GP5 bound to: 0 - type: integer 

Parameter C_USE_DIFF_RW_CLK_GP6 bound to: 0 - type: integer 

Parameter C_TRACE_PIPELINE_WIDTH bound to: 8 - type: integer 

Parameter C_EN_EMIO_TRACE bound to: 0 - type: integer 

Parameter C_EN_FIFO_ENET0 bound to: 0 - type: string 

Parameter C_EN_FIFO_ENET1 bound to: 0 - type: string 

Parameter C_EN_FIFO_ENET2 bound to: 0 - type: string 

Parameter C_EN_FIFO_ENET3 bound to: 0 - type: string 

Parameter C_TRACE_DATA_WIDTH bound to: 32 - type: integer 

Parameter C_USE_DEBUG_TEST bound to: 0 - type: integer 

Parameter C_DP_USE_AUDIO bound to: 0 - type: integer 

Parameter C_DP_USE_VIDEO bound to: 0 - type: integer 

INFO: [Synth 8-5534] Detected attribute (* keep = "true" *) [/home/hagi/ultra96base/ultra96base.srcs/sources_1/bd/design_1/ip/design_1_zynq_ultra_ps_e_0_0/hdl/zynq_ultra_ps_e_v3_3_1.v:2316]

INFO: [Synth 8-5534] Detected attribute (* keep = "true" *) [/home/hagi/ultra96base/ultra96base.srcs/sources_1/bd/design_1/ip/design_1_zynq_ultra_ps_e_0_0/hdl/zynq_ultra_ps_e_v3_3_1.v:2317]

INFO: [Synth 8-6157] synthesizing module 'BUFG_PS' [/home/hagi/Vivado/Vivado/2019.2/scripts/rt/data/unisim_comp.v:1299]

Parameter SIM_DEVICE bound to: ULTRASCALE_PLUS - type: string 

Parameter STARTUP_SYNC bound to: FALSE - type: string 

INFO: [Synth 8-6155] done synthesizing module 'BUFG_PS' (1#1) [/home/hagi/Vivado/Vivado/2019.2/scripts/rt/data/unisim_comp.v:1299]

INFO: [Synth 8-6157] synthesizing module 'PS8' [/home/hagi/Vivado/Vivado/2019.2/scripts/rt/data/unisim_comp.v:63170]

INFO: [Synth 8-6155] done synthesizing module 'PS8' (2#1) [/home/hagi/Vivado/Vivado/2019.2/scripts/rt/data/unisim_comp.v:63170]

WARNING: [Synth 8-689] width (4) of port connection 'EMIOSDIO0DATAOUT' does not match port width (8) of module 'PS8' [/home/hagi/ultra96base/ultra96base.srcs/sources_1/bd/design_1/ip/design_1_zynq_ultra_ps_e_0_0/hdl/zynq_ultra_ps_e_v3_3_1.v:4646]

WARNING: [Synth 8-689] width (4) of port connection 'EMIOSDIO0DATAENA' does not match port width (8) of module 'PS8' [/home/hagi/ultra96base/ultra96base.srcs/sources_1/bd/design_1/ip/design_1_zynq_ultra_ps_e_0_0/hdl/zynq_ultra_ps_e_v3_3_1.v:4647]

WARNING: [Synth 8-689] width (4) of port connection 'EMIOSDIO1DATAOUT' does not match port width (8) of module 'PS8' [/home/hagi/ultra96base/ultra96base.srcs/sources_1/bd/design_1/ip/design_1_zynq_ultra_ps_e_0_0/hdl/zynq_ultra_ps_e_v3_3_1.v:4659]

WARNING: [Synth 8-689] width (4) of port connection 'EMIOSDIO1DATAENA' does not match port width (8) of module 'PS8' [/home/hagi/ultra96base/ultra96base.srcs/sources_1/bd/design_1/ip/design_1_zynq_ultra_ps_e_0_0/hdl/zynq_ultra_ps_e_v3_3_1.v:4660]

WARNING: [Synth 8-7023] instance 'PS8_i' of module 'PS8' has 1015 connections declared, but only 957 given [/home/hagi/ultra96base/ultra96base.srcs/sources_1/bd/design_1/ip/design_1_zynq_ultra_ps_e_0_0/hdl/zynq_ultra_ps_e_v3_3_1.v:3836]

WARNING: [Synth 8-3848] Net dp_audio_ref_clk in module/entity zynq_ultra_ps_e_v3_3_1_zynq_ultra_ps_e does not have driver. [/home/hagi/ultra96base/ultra96base.srcs/sources_1/bd/design_1/ip/design_1_zynq_ultra_ps_e_0_0/hdl/zynq_ultra_ps_e_v3_3_1.v:335]

WARNING: [Synth 8-3848] Net irq_ipi_pl_0 in module/entity zynq_ultra_ps_e_v3_3_1_zynq_ultra_ps_e does not have driver. [/home/hagi/ultra96base/ultra96base.srcs/sources_1/bd/design_1/ip/design_1_zynq_ultra_ps_e_0_0/hdl/zynq_ultra_ps_e_v3_3_1.v:1355]

WARNING: [Synth 8-3848] Net irq_ipi_pl_1 in module/entity zynq_ultra_ps_e_v3_3_1_zynq_ultra_ps_e does not have driver. [/home/hagi/ultra96base/ultra96base.srcs/sources_1/bd/design_1/ip/design_1_zynq_ultra_ps_e_0_0/hdl/zynq_ultra_ps_e_v3_3_1.v:1356]

WARNING: [Synth 8-3848] Net irq_ipi_pl_2 in module/entity zynq_ultra_ps_e_v3_3_1_zynq_ultra_ps_e does not have driver. [/home/hagi/ultra96base/ultra96base.srcs/sources_1/bd/design_1/ip/design_1_zynq_ultra_ps_e_0_0/hdl/zynq_ultra_ps_e_v3_3_1.v:1357]

WARNING: [Synth 8-3848] Net irq_ipi_pl_3 in module/entity zynq_ultra_ps_e_v3_3_1_zynq_ultra_ps_e does not have driver. [/home/hagi/ultra96base/ultra96base.srcs/sources_1/bd/design_1/ip/design_1_zynq_ultra_ps_e_0_0/hdl/zynq_ultra_ps_e_v3_3_1.v:1358]

INFO: [Synth 8-6155] done synthesizing module 'zynq_ultra_ps_e_v3_3_1_zynq_ultra_ps_e' (3#1) [/home/hagi/ultra96base/ultra96base.srcs/sources_1/bd/design_1/ip/design_1_zynq_ultra_ps_e_0_0/hdl/zynq_ultra_ps_e_v3_3_1.v:282]

WARNING: [Synth 8-7023] instance 'inst' of module 'zynq_ultra_ps_e_v3_3_1_zynq_ultra_ps_e' has 1491 connections declared, but only 1487 given [/home/hagi/ultra96base/ultra96base.srcs/sources_1/bd/design_1/ip/design_1_zynq_ultra_ps_e_0_0/synth/design_1_zynq_ultra_ps_e_0_0.v:113]

INFO: [Synth 8-6155] done synthesizing module 'design_1_zynq_ultra_ps_e_0_0' (4#1) [/home/hagi/ultra96base/ultra96base.srcs/sources_1/bd/design_1/ip/design_1_zynq_ultra_ps_e_0_0/synth/design_1_zynq_ultra_ps_e_0_0.v:59]

WARNING: [Synth 8-3331] design zynq_ultra_ps_e_v3_3_1_zynq_ultra_ps_e has unconnected port dp_audio_ref_clk

WARNING: [Synth 8-3331] design zynq_ultra_ps_e_v3_3_1_zynq_ultra_ps_e has unconnected port irq_ipi_pl_0

WARNING: [Synth 8-3331] design zynq_ultra_ps_e_v3_3_1_zynq_ultra_ps_e has unconnected port irq_ipi_pl_1

WARNING: [Synth 8-3331] design zynq_ultra_ps_e_v3_3_1_zynq_ultra_ps_e has unconnected port irq_ipi_pl_2

WARNING: [Synth 8-3331] design zynq_ultra_ps_e_v3_3_1_zynq_ultra_ps_e has unconnected port irq_ipi_pl_3

WARNING: [Synth 8-3331] design zynq_ultra_ps_e_v3_3_1_zynq_ultra_ps_e has unconnected port saxihpc0_fpd_rclk

WARNING: [Synth 8-3331] design zynq_ultra_ps_e_v3_3_1_zynq_ultra_ps_e has unconnected port saxihpc0_fpd_wclk

WARNING: [Synth 8-3331] design zynq_ultra_ps_e_v3_3_1_zynq_ultra_ps_e has unconnected port saxihpc1_fpd_rclk

WARNING: [Synth 8-3331] design zynq_ultra_ps_e_v3_3_1_zynq_ultra_ps_e has unconnected port saxihpc1_fpd_wclk

WARNING: [Synth 8-3331] design zynq_ultra_ps_e_v3_3_1_zynq_ultra_ps_e has unconnected port saxihp0_fpd_rclk

WARNING: [Synth 8-3331] design zynq_ultra_ps_e_v3_3_1_zynq_ultra_ps_e has unconnected port saxihp0_fpd_wclk

WARNING: [Synth 8-3331] design zynq_ultra_ps_e_v3_3_1_zynq_ultra_ps_e has unconnected port saxihp1_fpd_rclk

WARNING: [Synth 8-3331] design zynq_ultra_ps_e_v3_3_1_zynq_ultra_ps_e has unconnected port saxihp1_fpd_wclk

WARNING: [Synth 8-3331] design zynq_ultra_ps_e_v3_3_1_zynq_ultra_ps_e has unconnected port saxihp2_fpd_rclk

WARNING: [Synth 8-3331] design zynq_ultra_ps_e_v3_3_1_zynq_ultra_ps_e has unconnected port saxihp2_fpd_wclk

WARNING: [Synth 8-3331] design zynq_ultra_ps_e_v3_3_1_zynq_ultra_ps_e has unconnected port saxihp3_fpd_rclk

WARNING: [Synth 8-3331] design zynq_ultra_ps_e_v3_3_1_zynq_ultra_ps_e has unconnected port saxihp3_fpd_wclk

WARNING: [Synth 8-3331] design zynq_ultra_ps_e_v3_3_1_zynq_ultra_ps_e has unconnected port saxi_lpd_rclk

WARNING: [Synth 8-3331] design zynq_ultra_ps_e_v3_3_1_zynq_ultra_ps_e has unconnected port saxi_lpd_wclk

WARNING: [Synth 8-3331] design zynq_ultra_ps_e_v3_3_1_zynq_ultra_ps_e has unconnected port sacefpd_awuser[15]

WARNING: [Synth 8-3331] design zynq_ultra_ps_e_v3_3_1_zynq_ultra_ps_e has unconnected port sacefpd_awuser[14]

WARNING: [Synth 8-3331] design zynq_ultra_ps_e_v3_3_1_zynq_ultra_ps_e has unconnected port sacefpd_awuser[13]

WARNING: [Synth 8-3331] design zynq_ultra_ps_e_v3_3_1_zynq_ultra_ps_e has unconnected port sacefpd_awuser[12]

WARNING: [Synth 8-3331] design zynq_ultra_ps_e_v3_3_1_zynq_ultra_ps_e has unconnected port sacefpd_awuser[11]

WARNING: [Synth 8-3331] design zynq_ultra_ps_e_v3_3_1_zynq_ultra_ps_e has unconnected port sacefpd_awuser[10]

WARNING: [Synth 8-3331] design zynq_ultra_ps_e_v3_3_1_zynq_ultra_ps_e has unconnected port sacefpd_awuser[9]

WARNING: [Synth 8-3331] design zynq_ultra_ps_e_v3_3_1_zynq_ultra_ps_e has unconnected port sacefpd_awuser[8]

WARNING: [Synth 8-3331] design zynq_ultra_ps_e_v3_3_1_zynq_ultra_ps_e has unconnected port sacefpd_awuser[7]

WARNING: [Synth 8-3331] design zynq_ultra_ps_e_v3_3_1_zynq_ultra_ps_e has unconnected port sacefpd_awuser[6]

WARNING: [Synth 8-3331] design zynq_ultra_ps_e_v3_3_1_zynq_ultra_ps_e has unconnected port sacefpd_aruser[15]

WARNING: [Synth 8-3331] design zynq_ultra_ps_e_v3_3_1_zynq_ultra_ps_e has unconnected port sacefpd_aruser[14]

WARNING: [Synth 8-3331] design zynq_ultra_ps_e_v3_3_1_zynq_ultra_ps_e has unconnected port sacefpd_aruser[13]

WARNING: [Synth 8-3331] design zynq_ultra_ps_e_v3_3_1_zynq_ultra_ps_e has unconnected port sacefpd_aruser[12]

WARNING: [Synth 8-3331] design zynq_ultra_ps_e_v3_3_1_zynq_ultra_ps_e has unconnected port sacefpd_aruser[11]

WARNING: [Synth 8-3331] design zynq_ultra_ps_e_v3_3_1_zynq_ultra_ps_e has unconnected port sacefpd_aruser[10]

WARNING: [Synth 8-3331] design zynq_ultra_ps_e_v3_3_1_zynq_ultra_ps_e has unconnected port sacefpd_aruser[9]

WARNING: [Synth 8-3331] design zynq_ultra_ps_e_v3_3_1_zynq_ultra_ps_e has unconnected port sacefpd_aruser[8]

WARNING: [Synth 8-3331] design zynq_ultra_ps_e_v3_3_1_zynq_ultra_ps_e has unconnected port sacefpd_aruser[7]

WARNING: [Synth 8-3331] design zynq_ultra_ps_e_v3_3_1_zynq_ultra_ps_e has unconnected port sacefpd_aruser[6]

WARNING: [Synth 8-3331] design zynq_ultra_ps_e_v3_3_1_zynq_ultra_ps_e has unconnected port test_adc_clk[3]

WARNING: [Synth 8-3331] design zynq_ultra_ps_e_v3_3_1_zynq_ultra_ps_e has unconnected port test_adc_clk[2]

WARNING: [Synth 8-3331] design zynq_ultra_ps_e_v3_3_1_zynq_ultra_ps_e has unconnected port test_adc_clk[1]

WARNING: [Synth 8-3331] design zynq_ultra_ps_e_v3_3_1_zynq_ultra_ps_e has unconnected port test_adc_clk[0]

WARNING: [Synth 8-3331] design zynq_ultra_ps_e_v3_3_1_zynq_ultra_ps_e has unconnected port test_adc_in[31]

WARNING: [Synth 8-3331] design zynq_ultra_ps_e_v3_3_1_zynq_ultra_ps_e has unconnected port test_adc_in[30]

WARNING: [Synth 8-3331] design zynq_ultra_ps_e_v3_3_1_zynq_ultra_ps_e has unconnected port test_adc_in[29]

WARNING: [Synth 8-3331] design zynq_ultra_ps_e_v3_3_1_zynq_ultra_ps_e has unconnected port test_adc_in[28]

WARNING: [Synth 8-3331] design zynq_ultra_ps_e_v3_3_1_zynq_ultra_ps_e has unconnected port test_adc_in[27]

WARNING: [Synth 8-3331] design zynq_ultra_ps_e_v3_3_1_zynq_ultra_ps_e has unconnected port test_adc_in[26]

WARNING: [Synth 8-3331] design zynq_ultra_ps_e_v3_3_1_zynq_ultra_ps_e has unconnected port test_adc_in[25]

WARNING: [Synth 8-3331] design zynq_ultra_ps_e_v3_3_1_zynq_ultra_ps_e has unconnected port test_adc_in[24]

WARNING: [Synth 8-3331] design zynq_ultra_ps_e_v3_3_1_zynq_ultra_ps_e has unconnected port test_adc_in[23]

WARNING: [Synth 8-3331] design zynq_ultra_ps_e_v3_3_1_zynq_ultra_ps_e has unconnected port test_adc_in[22]

WARNING: [Synth 8-3331] design zynq_ultra_ps_e_v3_3_1_zynq_ultra_ps_e has unconnected port test_adc_in[21]

WARNING: [Synth 8-3331] design zynq_ultra_ps_e_v3_3_1_zynq_ultra_ps_e has unconnected port test_adc_in[20]

WARNING: [Synth 8-3331] design zynq_ultra_ps_e_v3_3_1_zynq_ultra_ps_e has unconnected port test_adc_in[19]

WARNING: [Synth 8-3331] design zynq_ultra_ps_e_v3_3_1_zynq_ultra_ps_e has unconnected port test_adc_in[18]

WARNING: [Synth 8-3331] design zynq_ultra_ps_e_v3_3_1_zynq_ultra_ps_e has unconnected port test_adc_in[17]

WARNING: [Synth 8-3331] design zynq_ultra_ps_e_v3_3_1_zynq_ultra_ps_e has unconnected port test_adc_in[16]

WARNING: [Synth 8-3331] design zynq_ultra_ps_e_v3_3_1_zynq_ultra_ps_e has unconnected port test_adc_in[15]

WARNING: [Synth 8-3331] design zynq_ultra_ps_e_v3_3_1_zynq_ultra_ps_e has unconnected port test_adc_in[14]

WARNING: [Synth 8-3331] design zynq_ultra_ps_e_v3_3_1_zynq_ultra_ps_e has unconnected port test_adc_in[13]

WARNING: [Synth 8-3331] design zynq_ultra_ps_e_v3_3_1_zynq_ultra_ps_e has unconnected port test_adc_in[12]

WARNING: [Synth 8-3331] design zynq_ultra_ps_e_v3_3_1_zynq_ultra_ps_e has unconnected port test_adc_in[11]

WARNING: [Synth 8-3331] design zynq_ultra_ps_e_v3_3_1_zynq_ultra_ps_e has unconnected port test_adc_in[10]

WARNING: [Synth 8-3331] design zynq_ultra_ps_e_v3_3_1_zynq_ultra_ps_e has unconnected port test_adc_in[9]

WARNING: [Synth 8-3331] design zynq_ultra_ps_e_v3_3_1_zynq_ultra_ps_e has unconnected port test_adc_in[8]

WARNING: [Synth 8-3331] design zynq_ultra_ps_e_v3_3_1_zynq_ultra_ps_e has unconnected port test_adc_in[7]

WARNING: [Synth 8-3331] design zynq_ultra_ps_e_v3_3_1_zynq_ultra_ps_e has unconnected port test_adc_in[6]

WARNING: [Synth 8-3331] design zynq_ultra_ps_e_v3_3_1_zynq_ultra_ps_e has unconnected port test_adc_in[5]

WARNING: [Synth 8-3331] design zynq_ultra_ps_e_v3_3_1_zynq_ultra_ps_e has unconnected port test_adc_in[4]

WARNING: [Synth 8-3331] design zynq_ultra_ps_e_v3_3_1_zynq_ultra_ps_e has unconnected port test_adc_in[3]

WARNING: [Synth 8-3331] design zynq_ultra_ps_e_v3_3_1_zynq_ultra_ps_e has unconnected port test_adc_in[2]

WARNING: [Synth 8-3331] design zynq_ultra_ps_e_v3_3_1_zynq_ultra_ps_e has unconnected port test_adc_in[1]

WARNING: [Synth 8-3331] design zynq_ultra_ps_e_v3_3_1_zynq_ultra_ps_e has unconnected port test_adc_in[0]

WARNING: [Synth 8-3331] design zynq_ultra_ps_e_v3_3_1_zynq_ultra_ps_e has unconnected port test_adc2_in[31]

WARNING: [Synth 8-3331] design zynq_ultra_ps_e_v3_3_1_zynq_ultra_ps_e has unconnected port test_adc2_in[30]

WARNING: [Synth 8-3331] design zynq_ultra_ps_e_v3_3_1_zynq_ultra_ps_e has unconnected port test_adc2_in[29]

WARNING: [Synth 8-3331] design zynq_ultra_ps_e_v3_3_1_zynq_ultra_ps_e has unconnected port test_adc2_in[28]

WARNING: [Synth 8-3331] design zynq_ultra_ps_e_v3_3_1_zynq_ultra_ps_e has unconnected port test_adc2_in[27]

WARNING: [Synth 8-3331] design zynq_ultra_ps_e_v3_3_1_zynq_ultra_ps_e has unconnected port test_adc2_in[26]

WARNING: [Synth 8-3331] design zynq_ultra_ps_e_v3_3_1_zynq_ultra_ps_e has unconnected port test_adc2_in[25]

WARNING: [Synth 8-3331] design zynq_ultra_ps_e_v3_3_1_zynq_ultra_ps_e has unconnected port test_adc2_in[24]

WARNING: [Synth 8-3331] design zynq_ultra_ps_e_v3_3_1_zynq_ultra_ps_e has unconnected port test_adc2_in[23]

WARNING: [Synth 8-3331] design zynq_ultra_ps_e_v3_3_1_zynq_ultra_ps_e has unconnected port test_adc2_in[22]

WARNING: [Synth 8-3331] design zynq_ultra_ps_e_v3_3_1_zynq_ultra_ps_e has unconnected port test_adc2_in[21]

WARNING: [Synth 8-3331] design zynq_ultra_ps_e_v3_3_1_zynq_ultra_ps_e has unconnected port test_adc2_in[20]

WARNING: [Synth 8-3331] design zynq_ultra_ps_e_v3_3_1_zynq_ultra_ps_e has unconnected port test_adc2_in[19]

WARNING: [Synth 8-3331] design zynq_ultra_ps_e_v3_3_1_zynq_ultra_ps_e has unconnected port test_adc2_in[18]

WARNING: [Synth 8-3331] design zynq_ultra_ps_e_v3_3_1_zynq_ultra_ps_e has unconnected port test_adc2_in[17]

WARNING: [Synth 8-3331] design zynq_ultra_ps_e_v3_3_1_zynq_ultra_ps_e has unconnected port test_adc2_in[16]

WARNING: [Synth 8-3331] design zynq_ultra_ps_e_v3_3_1_zynq_ultra_ps_e has unconnected port test_adc2_in[15]

WARNING: [Synth 8-3331] design zynq_ultra_ps_e_v3_3_1_zynq_ultra_ps_e has unconnected port test_adc2_in[14]

WARNING: [Synth 8-3331] design zynq_ultra_ps_e_v3_3_1_zynq_ultra_ps_e has unconnected port test_adc2_in[13]

WARNING: [Synth 8-3331] design zynq_ultra_ps_e_v3_3_1_zynq_ultra_ps_e has unconnected port test_adc2_in[12]

WARNING: [Synth 8-3331] design zynq_ultra_ps_e_v3_3_1_zynq_ultra_ps_e has unconnected port test_adc2_in[11]

WARNING: [Synth 8-3331] design zynq_ultra_ps_e_v3_3_1_zynq_ultra_ps_e has unconnected port test_adc2_in[10]

WARNING: [Synth 8-3331] design zynq_ultra_ps_e_v3_3_1_zynq_ultra_ps_e has unconnected port test_adc2_in[9]

WARNING: [Synth 8-3331] design zynq_ultra_ps_e_v3_3_1_zynq_ultra_ps_e has unconnected port test_adc2_in[8]

WARNING: [Synth 8-3331] design zynq_ultra_ps_e_v3_3_1_zynq_ultra_ps_e has unconnected port test_adc2_in[7]

INFO: [Common 17-14] Message 'Synth 8-3331' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.

---------------------------------------------------------------------------------

Finished RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:53 . Memory (MB): peak = 2474.367 ; gain = 52.809 ; free physical = 158 ; free virtual = 1105

---------------------------------------------------------------------------------



Report Check Netlist: 

+------+------------------+-------+---------+-------+------------------+

|      |Item              |Errors |Warnings |Status |Description       |

+------+------------------+-------+---------+-------+------------------+

|1     |multi_driven_nets |      0|        0|Passed |Multi driven nets |

+------+------------------+-------+---------+-------+------------------+

---------------------------------------------------------------------------------

Start Handling Custom Attributes

---------------------------------------------------------------------------------

---------------------------------------------------------------------------------

Finished Handling Custom Attributes : Time (s): cpu = 00:00:06 ; elapsed = 00:00:57 . Memory (MB): peak = 2477.336 ; gain = 55.777 ; free physical = 143 ; free virtual = 1101

---------------------------------------------------------------------------------

---------------------------------------------------------------------------------

Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:06 ; elapsed = 00:00:57 . Memory (MB): peak = 2477.336 ; gain = 55.777 ; free physical = 143 ; free virtual = 1101

---------------------------------------------------------------------------------

Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.25 . Memory (MB): peak = 2487.242 ; gain = 0.000 ; free physical = 84 ; free virtual = 1092

INFO: [Project 1-570] Preparing netlist for logic optimization



Processing XDC Constraints

Initializing timing engine

Parsing XDC File [/home/hagi/ultra96base/ultra96base.srcs/sources_1/bd/design_1/ip/design_1_zynq_ultra_ps_e_0_0/design_1_zynq_ultra_ps_e_0_0_ooc.xdc] for cell 'inst'

Finished Parsing XDC File [/home/hagi/ultra96base/ultra96base.srcs/sources_1/bd/design_1/ip/design_1_zynq_ultra_ps_e_0_0/design_1_zynq_ultra_ps_e_0_0_ooc.xdc] for cell 'inst'

Parsing XDC File [/home/hagi/ultra96base/ultra96base.srcs/sources_1/bd/design_1/ip/design_1_zynq_ultra_ps_e_0_0/design_1_zynq_ultra_ps_e_0_0.xdc] for cell 'inst'

create_clock: Time (s): cpu = 00:00:04 ; elapsed = 00:00:12 . Memory (MB): peak = 2516.027 ; gain = 2.969 ; free physical = 72 ; free virtual = 1005

Finished Parsing XDC File [/home/hagi/ultra96base/ultra96base.srcs/sources_1/bd/design_1/ip/design_1_zynq_ultra_ps_e_0_0/design_1_zynq_ultra_ps_e_0_0.xdc] for cell 'inst'

Parsing XDC File [/home/hagi/ultra96base/ultra96base.runs/design_1_zynq_ultra_ps_e_0_0_synth_1/dont_touch.xdc]

Finished Parsing XDC File [/home/hagi/ultra96base/ultra96base.runs/design_1_zynq_ultra_ps_e_0_0_synth_1/dont_touch.xdc]

Completed Processing XDC Constraints



Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2516.027 ; gain = 0.000 ; free physical = 74 ; free virtual = 1013

INFO: [Project 1-111] Unisim Transformation Summary:

No Unisim elements were transformed.



Constraint Validation Runtime : Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:03 . Memory (MB): peak = 2516.027 ; gain = 0.000 ; free physical = 65 ; free virtual = 996

---------------------------------------------------------------------------------

Finished Constraint Validation : Time (s): cpu = 00:00:19 ; elapsed = 00:02:34 . Memory (MB): peak = 2516.027 ; gain = 94.469 ; free physical = 184 ; free virtual = 1049

---------------------------------------------------------------------------------

---------------------------------------------------------------------------------

Start Loading Part and Timing Information

---------------------------------------------------------------------------------

Loading part: xczu3eg-sbva484-1-e

INFO: [Synth 8-6742] Reading net delay rules and data

---------------------------------------------------------------------------------

Finished Loading Part and Timing Information : Time (s): cpu = 00:00:20 ; elapsed = 00:02:34 . Memory (MB): peak = 2516.027 ; gain = 94.469 ; free physical = 181 ; free virtual = 1049

---------------------------------------------------------------------------------

---------------------------------------------------------------------------------

Start Applying 'set_property' XDC Constraints

---------------------------------------------------------------------------------

Applied set_property DONT_TOUCH = true for inst/PS8_i. (constraint file  /home/hagi/ultra96base/ultra96base.srcs/sources_1/bd/design_1/ip/design_1_zynq_ultra_ps_e_0_0/design_1_zynq_ultra_ps_e_0_0.xdc, line 25).

Applied set_property DONT_TOUCH = true for inst. (constraint file  /home/hagi/ultra96base/ultra96base.runs/design_1_zynq_ultra_ps_e_0_0_synth_1/dont_touch.xdc, line 9).

---------------------------------------------------------------------------------

Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:20 ; elapsed = 00:02:36 . Memory (MB): peak = 2516.027 ; gain = 94.469 ; free physical = 177 ; free virtual = 1052

---------------------------------------------------------------------------------

---------------------------------------------------------------------------------

Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:20 ; elapsed = 00:02:42 . Memory (MB): peak = 2516.027 ; gain = 94.469 ; free physical = 138 ; free virtual = 1046

---------------------------------------------------------------------------------



Report RTL Partitions: 

+-+--------------+------------+----------+

| |RTL Partition |Replication |Instances |

+-+--------------+------------+----------+

+-+--------------+------------+----------+

---------------------------------------------------------------------------------

Start RTL Component Statistics 

---------------------------------------------------------------------------------

Detailed RTL Component Info : 

+---Registers : 

                1 Bit    Registers := 1     

---------------------------------------------------------------------------------

Finished RTL Component Statistics 

---------------------------------------------------------------------------------

---------------------------------------------------------------------------------

Start RTL Hierarchical Component Statistics 

---------------------------------------------------------------------------------

Hierarchical RTL Component report 

Module zynq_ultra_ps_e_v3_3_1_zynq_ultra_ps_e 

Detailed RTL Component Info : 

+---Registers : 

                1 Bit    Registers := 1     

---------------------------------------------------------------------------------

Finished RTL Hierarchical Component Statistics

---------------------------------------------------------------------------------

---------------------------------------------------------------------------------

Start Part Resource Summary

---------------------------------------------------------------------------------

Part Resources:

DSPs: 360 (col length:72)

BRAMs: 432 (col length: RAMB18 72 RAMB36 36)

---------------------------------------------------------------------------------

Finished Part Resource Summary

---------------------------------------------------------------------------------

---------------------------------------------------------------------------------

Start Cross Boundary and Area Optimization

---------------------------------------------------------------------------------

Warning: Parallel synthesis criteria is not met 

---------------------------------------------------------------------------------

Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:21 ; elapsed = 00:02:47 . Memory (MB): peak = 2516.027 ; gain = 94.469 ; free physical = 96 ; free virtual = 1033
Report RTL Partitions: 

| |RTL Partition |Replication |Instances |

Parent process (pid 3182) has died. This helper process will now exit

 

***vivado.log

#-----------------------------------------------------------
# Vivado v2019.2 (64-bit)
# SW Build 2708876 on Wed Nov  6 21:39:14 MST 2019
# IP Build 2700528 on Thu Nov  7 00:09:20 MST 2019
# Start of session at: Fri Mar 27 20:13:07 2020
# Process ID: 2368
# Current directory: /home/hagi
# Command line: vivado
# Log file: /home/hagi/vivado.log
# Journal file: /home/hagi/vivado.jou
#-----------------------------------------------------------
start_gui
open_project /home/hagi/ultra96base/ultra96base.xpr
Scanning sources...
Finished scanning sources
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/home/hagi/Vivado/Vivado/2019.2/data/ip'.
WARNING: [IP_Flow 19-3664] IP 'design_1_zynq_ultra_ps_e_0_0' generated file not found '/home/hagi/ultra96base/ultra96base.srcs/sources_1/bd/design_1/ip/design_1_zynq_ultra_ps_e_0_0/design_1_zynq_ultra_ps_e_0_0.dcp'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_1_zynq_ultra_ps_e_0_0' generated file not found '/home/hagi/ultra96base/ultra96base.srcs/sources_1/bd/design_1/ip/design_1_zynq_ultra_ps_e_0_0/design_1_zynq_ultra_ps_e_0_0_stub.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_1_zynq_ultra_ps_e_0_0' generated file not found '/home/hagi/ultra96base/ultra96base.srcs/sources_1/bd/design_1/ip/design_1_zynq_ultra_ps_e_0_0/design_1_zynq_ultra_ps_e_0_0_stub.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_1_zynq_ultra_ps_e_0_0' generated file not found '/home/hagi/ultra96base/ultra96base.srcs/sources_1/bd/design_1/ip/design_1_zynq_ultra_ps_e_0_0/design_1_zynq_ultra_ps_e_0_0_sim_netlist.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_1_zynq_ultra_ps_e_0_0' generated file not found '/home/hagi/ultra96base/ultra96base.srcs/sources_1/bd/design_1/ip/design_1_zynq_ultra_ps_e_0_0/design_1_zynq_ultra_ps_e_0_0_sim_netlist.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_1_clk_wiz_0_0' generated file not found '/home/hagi/ultra96base/ultra96base.srcs/sources_1/bd/design_1/ip/design_1_clk_wiz_0_0/design_1_clk_wiz_0_0.dcp'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_1_clk_wiz_0_0' generated file not found '/home/hagi/ultra96base/ultra96base.srcs/sources_1/bd/design_1/ip/design_1_clk_wiz_0_0/design_1_clk_wiz_0_0_stub.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_1_clk_wiz_0_0' generated file not found '/home/hagi/ultra96base/ultra96base.srcs/sources_1/bd/design_1/ip/design_1_clk_wiz_0_0/design_1_clk_wiz_0_0_stub.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_1_clk_wiz_0_0' generated file not found '/home/hagi/ultra96base/ultra96base.srcs/sources_1/bd/design_1/ip/design_1_clk_wiz_0_0/design_1_clk_wiz_0_0_sim_netlist.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_1_clk_wiz_0_0' generated file not found '/home/hagi/ultra96base/ultra96base.srcs/sources_1/bd/design_1/ip/design_1_clk_wiz_0_0/design_1_clk_wiz_0_0_sim_netlist.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_1_proc_sys_reset_0_0' generated file not found '/home/hagi/ultra96base/ultra96base.srcs/sources_1/bd/design_1/ip/design_1_proc_sys_reset_0_0/design_1_proc_sys_reset_0_0.dcp'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_1_proc_sys_reset_0_0' generated file not found '/home/hagi/ultra96base/ultra96base.srcs/sources_1/bd/design_1/ip/design_1_proc_sys_reset_0_0/design_1_proc_sys_reset_0_0_stub.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_1_proc_sys_reset_0_0' generated file not found '/home/hagi/ultra96base/ultra96base.srcs/sources_1/bd/design_1/ip/design_1_proc_sys_reset_0_0/design_1_proc_sys_reset_0_0_stub.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_1_proc_sys_reset_0_0' generated file not found '/home/hagi/ultra96base/ultra96base.srcs/sources_1/bd/design_1/ip/design_1_proc_sys_reset_0_0/design_1_proc_sys_reset_0_0_sim_netlist.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_1_proc_sys_reset_0_0' generated file not found '/home/hagi/ultra96base/ultra96base.srcs/sources_1/bd/design_1/ip/design_1_proc_sys_reset_0_0/design_1_proc_sys_reset_0_0_sim_netlist.vhdl'. Please regenerate to continue.
open_project: Time (s): cpu = 00:00:20 ; elapsed = 00:00:51 . Memory (MB): peak = 6495.891 ; gain = 226.148 ; free physical = 78 ; free virtual = 2369
update_compile_order -fileset sources_1
open_bd_design {/home/hagi/ultra96base/ultra96base.srcs/sources_1/bd/design_1/design_1.bd}
Adding component instance block -- xilinx.com:ip:zynq_ultra_ps_e:3.3 - zynq_ultra_ps_e_0
Adding component instance block -- xilinx.com:ip:clk_wiz:6.0 - clk_wiz_0
Adding component instance block -- xilinx.com:ip:proc_sys_reset:5.0 - proc_sys_reset_0
Adding component instance block -- xilinx.com:ip:xlconcat:2.1 - xlconcat_0
Successfully read diagram <design_1> from BD file </home/hagi/ultra96base/ultra96base.srcs/sources_1/bd/design_1/design_1.bd>
open_bd_design: Time (s): cpu = 00:00:09 ; elapsed = 00:00:25 . Memory (MB): peak = 6608.301 ; gain = 81.559 ; free physical = 75 ; free virtual = 2279
reset_run synth_1
launch_runs impl_1 -to_step write_bitstream
INFO: [IP_Flow 19-5642] Done with IP cache export for multiple IPs
[Fri Mar 27 20:18:29 2020] Launched design_1_zynq_ultra_ps_e_0_0_synth_1, design_1_clk_wiz_0_0_synth_1, design_1_proc_sys_reset_0_0_synth_1, synth_1...
Run output will be captured here:
design_1_zynq_ultra_ps_e_0_0_synth_1: /home/hagi/ultra96base/ultra96base.runs/design_1_zynq_ultra_ps_e_0_0_synth_1/runme.log
design_1_clk_wiz_0_0_synth_1: /home/hagi/ultra96base/ultra96base.runs/design_1_clk_wiz_0_0_synth_1/runme.log
design_1_proc_sys_reset_0_0_synth_1: /home/hagi/ultra96base/ultra96base.runs/design_1_proc_sys_reset_0_0_synth_1/runme.log
synth_1: /home/hagi/ultra96base/ultra96base.runs/synth_1/runme.log
[Fri Mar 27 20:18:30 2020] Launched impl_1...
Run output will be captured here: /home/hagi/ultra96base/ultra96base.runs/impl_1/runme.log
launch_runs: Time (s): cpu = 00:00:03 ; elapsed = 00:00:09 . Memory (MB): peak = 6659.102 ; gain = 37.801 ; free physical = 65 ; free virtual = 2276
0 Kudos
watari
Teacher
Teacher
412 Views
Registered: ‎06-16-2013

Hi @Pitto 

 

Did you run "Validate Design" to make sure your design before running implementation ?

If no, would you try it and make sure your design.

 

I guess your design has some problem.

 

Best regards,

0 Kudos