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pmaurice
Participant
Participant
533 Views
Registered: ‎10-16-2020

unable to connect xfft ip

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I want to use fft module but I have no clue how to connect that thing on the zynq ultrascale.

I have read 

https://www.xilinx.com/support/documentation/ip_documentation/xfft/v9_1/pg109-xfft.pdf

but like any xilinx documentation , it REALLY lacks of example and tutorials. 

I have found xapp1161.zip and dma_ex_fft_v2_0 but there is nothing to do with those old projects in vivado 2020.

PLEASE XILINX EMPLOYEE don't link me useless pdf documentation kind of bored of theses.

 

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pmaurice
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Participant
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Registered: ‎10-16-2020

I already know how to pull out the block IP and throw it into my design......

The things I don't know is how to connect the xFFT block to my zynq block design using mechanism such as DMA transfer because I don't have perfect knowledge of PS-PL AXI .

I already read pg109 but this document didn't helped me really, I mean I can go read it indefinably and I'll still be stuck here, most of the content is how to pull out the C-Model of the module to simulate the result of the module if you ever happen to make it work for real it allow to compare results.

Since I am not the first trying to attempt this, I have took a look on the forums for xFFT block to see what other did and unfortunately I haven't saw any relevant answer.

Is Xilinx is able to make the module work somehow ?????????? 

Do I need to get in touch with field application engineer to have a form of help ???

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3 Replies
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Registered: ‎01-22-2015

@pmaurice 

Like many Xilinx IP, you will find the Fast Fourier Transform (XFFT) IP in the Vivado IP catalog. 

FFT_IP.jpg

Clicking on the IP name in the catalog will bring up a Wizard that helps you setup the XFFT IP.

When you are done with the Wizard, Vivado will create templates that help you instantiate the XFFT IP into your design.  Vivado will also create a testbench that shows you how to use the XFFT IP.

This is not an easy IP to use.  You will need to read PG109 carefully to understand the many configuration options of this IP and to understand how AXI-Stream is used to write and read data from the IP.

Cheers,
Mark

 

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pmaurice
Participant
Participant
408 Views
Registered: ‎10-16-2020

I already know how to pull out the block IP and throw it into my design......

The things I don't know is how to connect the xFFT block to my zynq block design using mechanism such as DMA transfer because I don't have perfect knowledge of PS-PL AXI .

I already read pg109 but this document didn't helped me really, I mean I can go read it indefinably and I'll still be stuck here, most of the content is how to pull out the C-Model of the module to simulate the result of the module if you ever happen to make it work for real it allow to compare results.

Since I am not the first trying to attempt this, I have took a look on the forums for xFFT block to see what other did and unfortunately I haven't saw any relevant answer.

Is Xilinx is able to make the module work somehow ?????????? 

Do I need to get in touch with field application engineer to have a form of help ???

View solution in original post

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Rmccarty
Adventurer
Adventurer
392 Views
Registered: ‎09-05-2020

For ip with axi streams you can connect the stream in/out to an axi dma and then to an axi interconnect and finally to one of the ps hp slave interfaces. The hp interfaces have direct access to the ocm. Make sure to disable the cache for the ocm on the processor.

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