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azutter
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Registered: ‎08-21-2019

wrong readback and wrong default value from gateway_in axi4-lite with system generator

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Hi,

I have several gateway in block (registers) in my System Generator DSP-Core. Within the vivado block design, they are connected to the zynq core through axi4-lite.

Problem: On some registers the default value is wrong and on some registers the readback is wrong, it do not change if I write to it. See test output below.

I am using System Generator 2017.4.1 on Matlab Simulink 2016a. 

I have checked it with Vivado 2017.4.1 together with a Zynq 7030 and with Vivado 2019.1.3 together with a Zynq Ultrascale xczu4ev.

On the zynq 7030 the readback is working on all, but the default value is not working on all registers.

On the zynq ultrascale the readback and the default value both not working on all registers.

Both design are similar, main difference is the numberof channel instance. They are quite big, on ultrascale LUT usage is on 91% (Zynq 7030 61%).

Test Output from ultrascale on 0x93C0004C readback is wrong, on 0x93C00040 it is correct:

root@analog:~/tools# devmem2 0x93c0004c w 0x123
/dev/mem opened.
Memory mapped at address 0xf7b58000.
Value at address 0x93C0004C (0xf7b5804c): 0x0
Written 0x123; readback 0x123
root@analog:~/tools# devmem2 0x93c0004c
/dev/mem opened.
Memory mapped at address 0xf7d70000.
Value at address 0x93C0004C (0xf7d7004c): 0x0
root@analog:~/tools# devmem2 0x93c00040 w 0x234
/dev/mem opened.
Memory mapped at address 0xf7ce8000.
Value at address 0x93C00040 (0xf7ce8040): 0x8200
Written 0x234; readback 0x234
root@analog:~/tools# devmem2 0x93c00040
/dev/mem opened.
Memory mapped at address 0xf7a44000.
Value at address 0x93C00040 (0xf7a44040): 0x234

 

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azutter
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Registered: ‎08-21-2019

In the meantime I have implemented an axi4lite register interface with readback in sysgen manually and do not use the gateway in/out block with axi4lite anymore. This workaround works fine.

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azutter
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Registered: ‎08-21-2019

Just checked the axi bus connected to the DSP block with an ILA:

Write value 89 to address 88 shows as expected:

axi4lite_write_addr88_89.PNG

Read on address 88 shows value 89 on RDATA as expected: 

axi4lite_read_addr88.PNG

Write value 123 on address 84 as expected:

axi4lite_write_addr84_123.PNG

Read on address 84 shows value 0, not as expected:

axi4lite_read_addr84.PNG

 

Any suggestions? I think the problem is somewhere in the system generator DSP block. But I can't find anything special on registers that are not working..

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azutter
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Registered: ‎08-21-2019

Additional Information:

If I substitute the not working gateway in block by a constant block and then connect a gateway out block with the same address as the previous gateway in block, the read value is correct.

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azutter
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Registered: ‎08-21-2019

It seems to be a bug in system generator:

If I remove the gateway in block inside the subsystem and put it on the next higher level without changing the name or address, the readback from the register works.

Please help me, finding me a method that works. Because it is a big channelized design, I need to have the gateway blocks within the subsystems and distribute the addresses through subsystem mask adress offsets.

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azutter
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Registered: ‎08-21-2019

Please help me! Trying to solve this problem now since 7 days and get no response.

Have done a try with installing all the tools on Linux (Sysgen 2017.4.1 & Simulink 2016a), Vivado 2019.1.3.

Building under Linux does not help. Now the situation is different than under Windows, Gateway In registers that are working when building under Windows do not work when building in Linux and vice versa.

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azutter
Visitor
Visitor
376 Views
Registered: ‎08-21-2019

In the meantime I have implemented an axi4lite register interface with readback in sysgen manually and do not use the gateway in/out block with axi4lite anymore. This workaround works fine.

View solution in original post

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