03-07-2014 01:19 PM
First of all, I'm sorry for asking such a noob question. Unfortunately, I don't have any support offline.
I'm totally new to Xilinx Blockset in Simulink. My goal is to implement a controller on FPGA for HiL tests (this is a study project with an awful supervision). The controller has its transfer function:
C(z)=(b2*z^-2+b0)/(a2*z^-2+a1*z^-1+a0) - so a very basic IIR filter with sample time Ts=62.5 microsecons.
The main issue that I'm so concerned is that the delay and register blocks of Xilinx blockset have their latency equal to 1 clock cycle, but z^-1 blocks that I need for the controller should have the latency of Ts (i.e. 62.5 microseconds). In other words, I need to get "the previous sample" at the output of z^-1 v´block.
I know that it's possible to use counters to send the "enable" signals to the registers, thus implementing large latencies (in my case, for a latency of 62.5 microseconds I need to wait 6250 clock cycles if Tclk is 10 ns... a bit confusing). I'm not sure that it's a good solution.
I'd be glad if somebody could provide a tutorial for sampled-data controls design with XSG or give me some advices how to implement z-transfer functions with sample times much larger than the clock cycle in Xilinx Blockset.
03-10-2014 07:38 AM
I would recommend going through the 'Getting Started Trainings':
03-11-2014 10:30 AM
If you are just using System Generator to generate your bitststream then setup the clock location and speed on the system generator token. Then use that clock as base clock and derive all cloks in your design from this clock. For example if your clock is 100Mhz you can define a global variable in Matlab as 1/100e-6 like "clk_global".
In your input ports set the timing to "clk_global" and downsample the signals by 6250 to get your desired 62.5 us speed. You can then just use delays like you desire.
System Generator will generate the needed clock enables for those blocks automatically.
Hope I could help
03-13-2014 07:33 AM
I did everything as you adviced, but my xilinx IIR-filter seems to be unstable, although it should be stable. The magnitude of poles is 0.9998.., but I've used 64 bit denominator coefficients (for test purposes), so there are even no round-off errors ....
I also went through the Getting Started trainings, but they were not very useful for my current task (although quite useful in general).
The file with my filter is attached. May be it's not quite optimal filter structure, but at this stage I don't worry much about the efficiency.
I'm a bit in doubt, whether the z^(-1) blocks do really delay the signal by its sample time (and no by the clock period)... If I come to a working solution, I'll post it here too, because I searched a lot on the xilinx forums, but found no good reference (i.e. all models contain errors)
Best regards, histrix
03-13-2014 08:37 AM
SORRY, I don't know why, but I reopened the model in a new folder and it worked fine ... Btw, the previous file had a mistake (one of the adders should subtract), but previously it didn't also work with subtractor.. But newermind, the last (and more or less correct) model version is attached here. I hope it'll also compile fine...
03-13-2014 02:32 PM
The Sysgen Delay block always delays by the number of samples you specifiy in the block based on the input clock speed. It does exactly what you want.
I am currently at home and unable to open the .mdl file, but a few comments:
- Fixed Point might be a problem with IIR filter depending on the precision.
- Keep in mind the output type of the gains matter too and not just the denominator values. Especially in feedback path you will accumulate precision errors. You need to find the best precision, but still keep the bitwidth small.
- Multipliers/Gain should have a delay of at least one to be able to meet timing in most cases. especially if they are big
- There might be better filter structures for your design, which don't have precision problems. If you have the Digitial Filter Simulink block, then check the help for it. It shows multiple different strucutures which you can rebuild with Sysgen
- There are Filters in the Sysgen library. Try to check them out.
- Sysgen is bit and cycle true. That means the result in hardware is the same if clock speeds and inputs match your simulation
03-14-2014 04:03 AM
Thanks a lot, Markus!
many issues that you've mentioned are known to me. However, one issue is a source of trouble (although it is also known).
The problem is that if I downsample my input by, say 6250 (and set all design options to the values from your first post), then my delay block will introduce a latency of 6250 clock cycles.
But if I add some latency to multipliers/adders ("in order to meet the timing constraints"), then this latency will be also 6250 clock cycles (although only 3 clock cycles are in fact needed). Should I downsample before the delay block and then upsample again after the delay block? It should be clear that if every multiplier has the same or larger latency as the delay blocks, the filter won't work...
I'm trying to figure it out by myself, of course, but may be it's a known issue among specialists.
03-14-2014 06:03 AM
You can just put the delays directly on the gain/addusb blocks. There is no need to upsample/downsample anything within your filter
03-17-2014 04:57 AM
Here is my final filter, may be it'll be helpful for some other noob like me. See also the recommedations of Markus about fixed point, overflows etc.
In my opinion, it is better not to downsample but to keep the clock frequency as the base frequency for the whole design. Delays are still better to be implemented as counter-triggered registers, and the counter period is your filter sample period.
This allows to add enough latency to the multipliers/adders, since their "base frequency" remains the FPGA clock frequency, and hence the additional delays are small (2-3 clock cycles).
Sorry for many testing scopes, you may delete them. It is also assumed that the sample arrives at the 60th clock period (A/D conversion, interfaces may take the previous 60 clock periods).and leaves at the 66th clock period of the sample period (one sample period contains 6250 clock periods).
03-17-2014 02:25 PM
The down samples are internally implemented the same way.
Sysgen uses clock enables. The block itself still runs at max speed, but is just only enabled every X samples.
There are no additional delays/registers used. Its just a matter of what you like more.
03-18-2014 10:48 PM
You can refer this Artical
02-23-2016 10:59 PM - edited 02-23-2016 11:04 PM
Except the 3rd and 4th post from you, the remaining are really helpful a lot. When coming to these two posts, actually i would like to support histrix, as i verified the results through the simulation using wavescope in it. i sampled the data at the gatewayin at 100MHZ, sent to the downsample block and delay2 block of 4 cycles as shown in figure below. And after downsampling to the 10 MHZ i sent to the CMult block with gain 1 and delay of 4 cycles.
As per your perception, "The down samples are internally implemented the same way", the both delays has to be same, but it is not like that when we checked through the wavescope (clock signal= 10ns). The delay2 block is delayed the signal 40 nanosec(4X10ns) where as the Cmult block delays the signal 400 nanosec(4X100ns), though both have delay of 4 cycles.
Hence, we can conclude that the delay depends on at what sampe rate that blcok excecutes. so if this much delay happened at the o/p of cmult the filter won't work. so we need to follow some other circuitry to deal with it. hence i followed similar to the histrix procedure, though, for my control algorithm it seems much complex to deal with it. if any other easy methods are there, it is worth to share.