by Uttara Kumar Sr. Product Marketing Manager, Software & AI and Frédéric Rivoallon Product Manager Xilinx HLS and XRM
In another leap forward in our commitment to supporting open-source initiatives that help empower the developer and research communities at large to harness the benefits of adaptive computing, we’ve made the exciting move to open access to the front-end of our Vitis HLS (high level synthesis) on GitHub, the world’s largest development platform and open community for building and sharing software code. The Vitis HLS tool allows C, C++, and OpenCL™ functions to be deployed onto the device logic fabric and RAM/DSP blocks. Making the Vitis HLS front-end available on GitHub opens a new world of possibilities for researchers, developers and compiler enthusiasts to tap into the Vitis HLS technology and modify it for the specific needs of their applications.
We’ve consistently enhanced our HLS technology for over 10 years to deliver increased design productivity for hardware developers and make the power of Xilinx adaptable platforms more broadly accessible to software and application developers without hardware design experience. With the front-end of Vitis HLS now open source and available to all on GitHub, software and hardware developers have the flexibility to use the standard Clang/LLVM infrastructure and customize the design flow to:
Add support for new high-level languages beyond C/C++ and OpenCL
Add new domain-specific optimization pragmas or compiler directives
Customize the transformations to the LLVM IR (new LLVM passes)
The C/C++ to RTL synthesis flow in Vitis HLS consists of 2 main components –  Front-end: This component parses the code expressed in C/C++ or OpenCL, applies front-end and middle-end transformations using the Clang/LLVM tool chain  Back-end: This phase takes an LLVM IR input and performs FPGA-specific lowering and scheduling till the final step, RTL generation
Beyond enabling the Clang/LLVM flow, this project offers:
A framework for pragma support and hardware synthesizability checks
A method to map inherently sequential C code onto a spatial hardware architecture
A gateway to the Vitis Unified Software Platforms and hence access to the associated flows and libraries
Learn how our ecosystem partner Silexica and the research community at University of Illinois at Urbana Champaign (UIUC), Imperial College London and Hong Kong University of Science and Technology are leveraging the Vitis HLS front-end to extend its capabilities and aid their research projects.
Silexica extends Vitis HLS Front-end Optimizations with the SLX Plugin
“Open sourcing the front-end of Vitis HLS empowers the FPGA research and Ecosystem Partner community to extend, customize and even further optimize the HLS compilation process” said Jordon Inkeles, VP of Product at Silexica “This new open source initiative from Xilinx also comes with the radically new ‘injection use model’ for Vitis HLS that makes it possible to inject custom third-party code transformations, or even use a completely custom Clang compiler front-end”
In close collaboration with Xilinx, Silexica has created a plugin, namely the SLX Plugin, that extends Vitis HLS 2020.2 code transformations, leveraging the new injection use model. The SLX Plugin is an HLS compiler add-on that helps improve Vitis HLS latency and throughput results by providing a new Loop Interchange directive. This is the first of many planned HLS optimization directives from Silexica. The plugin can be used as a pure standalone addition to Vitis HLS, or in combination with Silexica’s SLX FPGA tool to benefit from its deep code analysis, automatic design exploration, and optimal directive identification and tuning capabilities.
Dr. Deming Chen, Abel Bliss Professor of Engineering
Hanchen Ye, Research Assistant
“We received the open-source package in advance through the collaboration on Xilinx Adaptive Compute Cluster (XACC) program at UIUC. Using the interface provided by the package, we can conveniently customize and integrate new Clang pragmas and LLVM passes into Vitis HLS to implement and evaluate our research ideas. The ability to leverage LLVM into the Vitis HLS flow is enabling new possibilities in many ways. In addition, this open-source Vitis HLS frontend will significantly boost the growth of the HLS open-source community. We are excited to be part of it”.
Imperial College London
Jianyi Cheng, PhD candidate, Circuits and Systems (CAS) Group
“Feeding the code into Vitis HLS is problematic for HLS tool designers like me when transforming LLVM IR back to C code, including pragmas. The new Vitis HLS front-end has significantly helped integrate our tool Dynamic and Static Scheduling (DASS) into the HLS flow. For instance, the open-sourced front-end allows us to directly do program analysis and transformation and pragma insertion in LLVM”
Hong Kong University of Science and Technology (HKUST)
Tingyuan Liang, PhD candidate, Reconfigurable Computing Systems Lab
“From our perspective, developing a comprehensive HLS tool requires tremendous engineering efforts and is one of the gaps between academia and industry. Xilinx's generous opening of the commercial HLS frond-end, which can be coupled with Vitis HLS, provides flexible APIs and readable source code from parsing to IR optimization. It releases us from handling the detailed implementation, enables us to tackle problems in practical application scenarios and helps us evaluate our ideas efficiently. For the HLS community, we believe that this open-source project will boost the innovation significantly since it allows users to easily customize the tool for their specific demands”
The Vitis HLS Front-end is being leveraged in 2 developing projects at HKUST:
Project 1 - High-Efficiency Automatic Optimization Pass Phase Ordering: In this project, the optimal order of the provided optimization passes in the open-source frond-end, based on the features of the input source code, will be searched via machine-learning and heuristic algorithms, for the improvement of performance and resource consumption.
Project 2 - Multi-FPGA HLS: In this project, the IR code generated by the open-source front-end will be analyzed by the model of performance and resource, and automatically partitioned into sub-modules optimized for the application of multiple FPGAs interconnected with network or DDR memory.
Ready to Get Started?
The source code for the Vitis HLS front-end is available on the Xilinx GitHub repository. The repository shares 3 examples that demonstrate how to use and customize the flow that includes building a custom LLVM pass