Showing results for 
Search instead for 
Did you mean: 

Updated DPU Reference Design

Xilinx Employee
Xilinx Employee
1 0 2,113

The Xilinx DPU reference design was recently updated to support the latest DPU with all configurations from B512 to B4096. It now supports more layers such as Depthwise Conv, Relu6, Average Pooling and Softmax, all in hardware.

These changes increases the ability of the DPU to support newer models, including Mobilenet.

You can download the reference design from here (.zip file)

We recommend using the reference guide in conjunction with the updated DPU IP Product Guide PG338, available here (PDF)

Please use this reference design with the latest DNNDK v3.0. (.zip file)

Table 7 of PG338 has updated information about  hardware constraints of supported layers which is useful as a guide for custom model deployment.