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e_ensafi
Explorer
Explorer
439 Views
Registered: ‎08-13-2020

AIE - Vitis 2020.2 XCLBIN Generation Very Slow

Compared to v2020.1, generating an xclbin in v2020.2 is significantly slower.  Is this known to be the case?

After what was already an excruciatingly long time, I am now stuck at "Phase 4.1 Global Iteration 0" with Vivado pegging multiple cores of my CPUs on a dual 18-core Xeon system with 128 GB RAM.

There are lots of critical warnings too, like this one:

CRITICAL WARNING: [VPL 19-4299] Failed to copy '.../link/vivado/vpl/.local/hw_platform/prj/xilinx_vck190_es1_base.gen/sources_1/bd/xilinx_vck190_es1_base/ip/xilinx_vck190_es1_base_noc_lpddr4_0/bd_0/ip/ip_1/ip_0/temp/ddr_rd_vref_cal.c' to '...'
 
The exact same application builds just fine under v2020.1.
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florentw
Moderator
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Registered: ‎11-09-2015

Hi @e_ensafi 

I would not expect 2020.2 to be slower than 2020.1. If you can share a test case we can have a look.

Else maybe could you at least share the log files for the same project in 2020.1 an 2020.2?


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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e_ensafi
Explorer
Explorer
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Registered: ‎08-13-2020

It's becoming increasingly difficult for me to create meaningful test cases as my application continues to grow in complexity.  However, I can tell you with certainty that the Vitis "v++ --link" step took under 40 minutes in 2020.1, but it took over 1 hour and 20 minutes in 2020.2.

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florentw
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Moderator
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Registered: ‎11-09-2015

HI @e_ensafi 

And would you be able to share the v++ logs?


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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e_ensafi
Explorer
Explorer
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Registered: ‎08-13-2020

Possibly.  I will have to re-run the 2020.1 version to make sure I have the correct logs.  At this point, I have migrated to 2020.2 and have not looked back, other than than this speed issue.  Let me see if I can pull something together by the end of the week, but I have bigger fish to fry at the moment.

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