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Douae
Newbie
Newbie
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Registered: ‎10-05-2020

Building RTL kernel application memory access error

Hello, 

I am attempting to build and run an RTL kernel HW emulation, when I try to build I get the error printed below: 

/opt/xilinx/Vivado/2020.1/bin/loader: Zeile 286: 10771 Speicherzugriffsfehler  "$RDI_PROG" "$@"

Speicherzugrifffehler: which means memory access failure in German 

I have followed the RTL kernel wizard flow to create the interfaces, instantiated my verilog module in the generated RTL sources, compiled and synthesized the design and everything seems fine. I was wondering what could be the source of the error, any help in this regard would be appreciated ! 

 

The following is the detailed message I get: 

 

--include /opt/xilinx/Vivado/2020.1/tps/boost_1_64_0 -L sim_clk_gen_v1_0_2 -L xil_defaultlib -L axi_lite_ipif_v3_0_4 -L axi_intc_v4_1_14 -L xlconcat_v2_1_3 -L xlconstant_v1_1_7 -L lib_cdc_v1_0_2 -L proc_sys_reset_v5_0_13 -L interrupt_control_v3_1_4 -L axi_gpio_v2_0_23 -L generic_baseblocks_v2_1_0 -L axi_infrastructure_v1_1_0 -L axi_register_slice_v2_1_21 -L fifo_generator_v13_2_5 -L axi_data_fifo_v2_1_20 -L axi_crossbar_v2_1_22 -L axi_protocol_converter_v2_1_21 -L axi_clock_converter_v2_1_20 -L unisims_ver -L unimacro_ver -L secureip -L xpm -sv_root . -sc_lib libdpi.so --snapshot emu_wrapper_behav xil_defaultlib.emu_wrapper xil_defaultlib.glbl -log elaborate.log --include /opt/xilinx/Vivado/2020.1/data/simmodels/xsim/2020.1/lnx64/6.2.0/ext/protobuf/include -ignore_assertions --debug sc

Using 8 slave threads.

Starting static elaboration

/opt/xilinx/Vivado/2020.1/bin/loader: Zeile 286: 10771 Speicherzugriffsfehler  "$RDI_PROG" "$@"

segfault in /opt/xilinx/Vivado/2020.1/bin/unwrapped/lnx64.o/xelab -exec xelab -wto 22158b8f9d0445d8abc5811294bf629e --incr --debug typical --relax --mt 8 -sv_root /opt/xilinx/Vivado/2020.1/data/simmodels/xsim/2020.1/lnx64/6.2.0/ext/protobuf -sc_lib libprotobuf.so --include /opt/xilinx/Vivado/2020.1/data/simmodels/xsim/2020.1/lnx64/6.2.0/ext/protobuf/include -sv_root /opt/xilinx/Vivado/2020.1/data/xsim/ip/xtlm -sc_lib libxtlm.so --include /opt/xilinx/Vivado/2020.1/data/xsim/ip/xtlm/include -sv_root /opt/xilinx/Vivado/2020.1/data/xsim/ip/xtlm_simple_interconnect_v1_0 -sc_lib libxtlm_simple_interconnect_v1_0.so --include /opt/xilinx/Vivado/2020.1/data/xsim/ip/xtlm_simple_interconnect_v1_0/include -sv_root /opt/xilinx/Vivado/2020.1/data/xsim/ip/common_cpp_v1_0 -sc_lib libcommon_cpp_v1_0.so --include /opt/xilinx/Vivado/2020.1/data/xsim/ip/common_cpp_v1_0/include -sv_root /opt/xilinx/Vivado/2020.1/data/xsim/ip/emu_perf_common_v1_0 -sc_lib libemu_perf_common_v1_0.so --include /opt/xilinx/Vivado/2020.1/data/xsim/ip/emu_perf_common_v1_0/include --

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