11-21-2020 12:07 PM - edited 11-21-2020 12:08 PM
I'm trying to create resnet50 working model on my 104 fpga (I wish to do the full process on my own, from the model-zoo -----> board).
Until now i managed to create the .elf file. I also have gv file.
I saw in the predefined example of resnet 50 that there is also a program which called resnet50 (i guess it's code is https://github.com/Xilinx/Vitis-AI/tree/master/VART/samples/resnet50/src).
1) Is there any kind of "automation" for creating this cc file?
I wonder, what if i would try to create a different model (which is not the same as one of your samples). Would I need to create it on my own?
2) what is exactly this gv file i got from the compilation? (I got it with the elf file).
11-22-2020 10:16 PM
There's no automation of creating the main.cc. Based on the provided one, you can make necessary edits to suit your own application. It basically demonstrates how to call the the unified high-level runtime API for both cloud and edge.
The .gv should be a transformed graph in DOT format, which you can convert to a JPEG file.
11-22-2020 11:31 PM
I understand about the cpp.
Question about the fpga itself in the process of the vitis-ai:
So i'm still a bit confused. Where is the bit stream file i usually upload to the fpga?
Is the elf includes the bitstream? (is there any bitsream file at all?)
11-24-2020 01:24 AM
DPU ELF file encapsulates the DPU instruction codes and parameters for the network model.
The DPU RTL kernel is integrated via Vitis (see https://github.com/Xilinx/Vitis-AI/tree/master/DPU-TRD/prj/Vitis). You get output files like sd_card.img to boot the edge board. dpu.xclbin is called by XRT and get loaded to hardware.