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s3159
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Registered: ‎11-04-2020

DPU的IP核

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问一下Vivado里有没有DPU的IP核

我想在例程的Vitis-AI上扩展板子上现有的一些硬件设备

但是Vitis-AI相关例程只给了一个SD卡文件,所以我想在我现有的Vivado工程上加DPU 的IP核来实现深度学习

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graces
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Registered: ‎07-16-2008

可能存在版本兼容的问题,可尝试1.2版本的DPU TRD。

https://github.com/Xilinx/Vitis-AI/tree/v1.2.1/DPU-TRD

另外,更推荐用Vitis Flow,验证测试会更完备一些。

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graces
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DPU IP可参考:https://github.com/Xilinx/Vitis-AI/tree/master/dsa/DPU-TRD/dpu_ip

 

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s3159
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我下载了这个IP和和附带的tcl文件,用tcl生成工程后run synthesis 有下面的错误

 

WARNING: [IP_Flow 19-395] Problem validating against XML schema: see 'xilinx:componentInstanceExtensions' : Bad end of element
CRITICAL WARNING: [IP_Flow 19-5097] Unable to determine VLNV from IP file; verify it has the correct syntax: c:/Users/Administrator/Desktop/Vitis-AI-master/DPU-TRD/prj/Vivado/srcs/top/ip/top_dpu_0/xci/sfm/fp_exp/fp_exp.xci
ERROR: [IP_Flow 19-3505] IP Generation error: Failed to generate IP 'hier_dpu/dpu'. Failed to create IP subcores.
ERROR: [IP_Flow 19-98] Generation of the IP CORE failed.
Failed to generate IP 'hier_dpu/dpu'. Failed to create IP subcores.
ERROR: [BD 41-1030] Generation failed for the IP Integrator block hier_dpu/dpu

1609729620(1).png
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graces
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附带的Tcl是哪个文件?DPU TRD里的吗?

另外,master branch对应的是Vivado 2020.2.

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s3159
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DPU-TRD\prj\Vivado\scripts的trd_prj.tcl文件

我是vivado 2020.1,是版本的问题吗

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graces
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Registered: ‎07-16-2008

可能存在版本兼容的问题,可尝试1.2版本的DPU TRD。

https://github.com/Xilinx/Vitis-AI/tree/v1.2.1/DPU-TRD

另外,更推荐用Vitis Flow,验证测试会更完备一些。

-----------------------------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs.
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s3159
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Registered: ‎11-04-2020

请问您遇到过synthesis一直卡在这的情况吗,我等了半天都没反应,之前用其他的例程很快就完成了

1609831612(1).png
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zhijiexu
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Registered: ‎09-29-2020

hi, @s3159 

多久呢,0.5-3h都是正常的,取决与电脑配置

希望对你有帮助

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s3159
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大概半小时多

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s3159
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Registered: ‎11-04-2020

昨天我等了四五个小时还是不行

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s3159
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没事了,刚才半小时就跑完了,不知道昨天怎么回事

 

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s3159
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Registered: ‎11-04-2020

请问这种情况怎么解决呢,我是AXU4EV-E的开发板,这个工程是ZCU-102的

我查资料说是他的RAM资源不够用

[DRC UTLZ-1] Resource utilization: LUT as Distributed RAM over-utilized in Top Level Design (This design requires more LUT as Distributed RAM cells than are available in the target device. This design requires 91116 of such cell types but only 57600 compatible sites are available in the target device. Please analyze your synthesis results and constraints to ensure the design is mapped to Xilinx primitives as expected. If so, please consider targeting a larger device. Please set tcl parameter "drc.disableLUTOverUtilError" to 1 to change this error to warning.)
[DRC UTLZ-1] Resource utilization: LUT as Logic over-utilized in Top Level Design (This design requires more LUT as Logic cells than are available in the target device. This design requires 103849 of such cell types but only 87840 compatible sites are available in the target device. Please analyze your synthesis results and constraints to ensure the design is mapped to Xilinx primitives as expected. If so, please consider targeting a larger device. Please set tcl parameter "drc.disableLUTOverUtilError" to 1 to change this error to warning.)
[DRC UTLZ-1] Resource utilization: LUT as Memory over-utilized in Top Level Design (This design requires more LUT as Memory cells than are available in the target device. This design requires 94293 of such cell types but only 57600 compatible sites are available in the target device. Please analyze your synthesis results and constraints to ensure the design is mapped to Xilinx primitives as expected. If so, please consider targeting a larger device. Please set tcl parameter "drc.disableLUTOverUtilError" to 1 to change this error to warning.)
[DRC UTLZ-1] Resource utilization: RAMB18 and RAMB36/FIFO over-utilized in Top Level Design (This design requires more RAMB18 and RAMB36/FIFO cells than are available in the target device. This design requires 260 of such cell types but only 256 compatible sites are available in the target device. Please analyze your synthesis results and constraints to ensure the design is mapped to

 

 

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sitting
Voyager
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Registered: ‎05-04-2014

Hi,

你的dpu設定要調整一下,可以貼出你的dpu設定

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s3159
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Registered: ‎11-04-2020

这是DPU设置,我用官方给SD文件实验的时候用dexplorer -w也看了一下

4b64a083188c2ec90ea56e904a040ce.png
1609940138(1).png
1609940107(1).png
1609940124(1).png
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sitting
Voyager
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Hi,

4EV的URAM沒這麼大,可以試試將Number of DPU core改成1,RAM Usage改成low,Arch of DPU可以改成B2304, DSP Usage可以改成High。

我自己也有用4EV跑過,不過我是用Vitis flow,提供dpu_conf.vh給你參考

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s3159
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大佬还是不行,现在只报这个错误

[DRC UTLZ-1] Resource utilization: RAMB18 and RAMB36/FIFO over-utilized in Top Level Design (This design requires more RAMB18 and RAMB36/FIFO cells than are available in the target device. This design requires 260 of such cell types but only 256 compatible sites are available in the target device. Please analyze your synthesis results and constraints to ensure the design is mapped to Xilinx primitives as expected. If so, please consider targeting a larger device.)

我试过改那些设置这个错误消不掉

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sitting
Voyager
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Registered: ‎05-04-2014

Hi,

Block RAM還是超過,你的DPU summary是否能重新貼出來嗎?然後vivado的utilization(像下面這張圖)也可以貼出來嗎?

你的block design中還有什麼ip會用到block ram?

utilitzation.PNG

 

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s3159
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那2个summary有一个是按照您说的设置,另一个是B1600,RAM usege是HIGH的

后面的utilization应该没区别,两次的error报错的大小是一样的

1610020046(1).png
1610020062(1.png
1610020510(1).png
1610020575(1).png
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s3159
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我用的就是github上ZCU102的DPU IP核的工程,还没加别的部分

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sitting
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Hi, 

你的DPU 使用到的block ram超過了,4EV有URAM可以開。你的URAM use per DPU有設定嘛?

 

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graces
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如@sitting所回复的,目前的问题是RAM资源超过了目标器件所能提供的,解决方法是减小RAM的使用率。可尝试更小的DPU arch,如B1152,或者设成low RAM usage。

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s3159
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我现在更改了URAM,综合和实现都过了,petalinux工程还在编译中

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s3159
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我现在更改了 uram,综合和实现通过了,请问您遇到过这个问题吗?

原因是我更改了ZYNQ ultrascale+ ip核的时钟频率,百度到的解释是DPU部分无法自动匹配时钟频率

我按照他们的方法试过将删除重新创建这些接口,还是不行

$1P)`K][$S]9{)G]6QAB%QL.png
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sitting
Voyager
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Hi,

我自己的作法都是將33.333改成33.333333,這樣clock就會變成100 MHz

clock.PNG

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s3159
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大佬,我现在的问题是调用了他的一个DPU IP核,这个IP的时钟本来应该是自动设置成时钟输入的,但是现在我的工程里不能匹配,所以我只要一改时钟就会出问题

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s3159
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大佬,我重新把那个IP核重新调了一些就好了,,,

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zhangna
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Registered: ‎06-22-2021

请问您这个问题解决了吗?我也遇到了同样的问题,vivado2020.1下报同样的错误。是软件版本的问题吗?

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s3159
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你可以试一下按照他的工程自己重新搭一个,我记得当初好像是这么弄的

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