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Explorer
Explorer
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Registered: ‎05-03-2018

DPU Configuration Parameter Description

Hi,The DPU1152,4*12*12, What does parameter 4 mean? 

    I think 4 means that the parameter is quantized to 4bit, right?

1560755309(1).png

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Xilinx Employee
Xilinx Employee
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Registered: ‎12-09-2015

Re: DPU Configuration Parameter Description

(^^)/

 

Please see PG338 (v2.0) p.22:

Capture.PNG

Capture.PNG

 

Thus, the 1st number refers to the pixel parallelism; the 2nd number refers to the input channel parallelism; and the 3rd number refers to the output channel parallelism.

 

 

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Explorer
Explorer
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Registered: ‎05-03-2018

Re: DPU Configuration Parameter Description

@lvalena   thanks for your answer,I know this,but I am not sure the pixel parallelism mean,

I guess it is a clock that calculates four pixels  or  One pixel is represented by four bits,i am not sure.

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Xilinx Employee
Xilinx Employee
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Registered: ‎12-09-2015

Re: DPU Configuration Parameter Description

(^^)/

 

Consider the VGG16 architecture.

Capture.PNG

Capture.PNG

The first layer, "Conv 1-1" has 3 input channels and 64 output channels. The second layer, "Conv 1-2" has 64 input channels and 128 output channels. The "pixels" are the elements in each blob (or tensor). Thus, "Conv 1-1" has 224x224x3 input pixels to process and generates 224x224x64 output "pixels" (or blob/tensor elements).

 

The DPU "pixel parallelism" refers to the number of *output* blob/tensor elements it can calculate per clock cycle.

 

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