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Observer
Observer
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Registered: ‎08-10-2020

DPU Device Tree - Questions

Hello,

I have a generel question about the settings for the device-tree for the DPU. Sadly, it is a little bit unclear on how to set these, but I was able to find some information online. 

It would be great if someone with better knowledge could comment and fill out the missing gaps to this post. Some of the question might be very basic, but I could not find any direct answre to this. I am completly new to the device-tree Syntax.

I mostly rely on this Document: Zynq DPU v.3.2 IP Product Guide 

 

When checking for the device-tree the following is shown:

&amba { ...

              dpu {
                       compatible = "xilinx,dpu";
                       base-addr = <0x8f000000>;//CHANGE THIS ACCORDING TO YOUR DESIGN
                       dpucore {
                                       compatible = "xilinx,dpucore";
                                       interrupt-parent = <&intc>;
                                       interrupts = <0x0 106 0x1 0x0 107 0x1>;
                                       core-num = <0x2>; };
                                     };

                       softmax {
                                       compatible = "xilinx, smfc";
                                       interrupt-parent = <&intc>;
                                       interrupts = <0x0 110 0x1>;
                                       core-num = <0x1>;
                                    .... }


1. The name of the nodes "dpu" and "dpucore" are "free" to chose? Or do they have to present in the BD-Design in Vivado? Where do these names origin from?
2. The base-address can be seen in the Adress Editor in Vivado. In older version it was mentioned that the DPU could not be placed at an other address - is this still the case?
3. In the DPU Core the Interrupt-Number must be set. Sadly, I could not find a Document where Interrupt Numbers are explained, but I found a Xilinx Forum Post  on this forum explaining them. 
Is there a fitting document to find the documentation for the Interrupt Number? 

4. The Last number in the three tuple interrupt depicts wether the interrupt is rising edge, falling edge, level high or level low. In the shown example from the DPU Product Guide, it is set to 0x1 - which means Rising Edge. On page 13 it is shown that the dpu_interrupt is active_high - how can I set or know if my Interrupt is rising edge or level high? When I implemented the TRD for a DPU from the zcu102 example (like it is mentioned in the product guide) it was automatically set to LEVEL HIGH - and should therefore be 0x4 at the end?
5. I looked at some other dpu device-trees and they had others keys in it like: reg = <0x0 0x8f000000 0x0 0x700> and memory = <0x60000000 0x80000000> how do I know if need these, too and if I need them how do I know the corresponding values?
6. Lastly, the softmax core is implemented too, but isn't it missing an address? How can I know the adress of my sofmtax core if it is not shown in the Adress editor in vivado? 


Thank you for helping and answering, I hope that this thread will help others, too.


Greetings,

Kevin



 

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4 Replies
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Explorer
Explorer
178 Views
Registered: ‎06-09-2015

Hello Kevin,

I would like to add few points which might help you on your development!

You can get most of your questions answer at DPU Integration Guide (forked version) regarding to interrupt number, rising edge/falling edge,  and you are already reviewing PG338 [see Table 19: Device Tree Fields again] which covers all questions. And finally as of the documentation and design flow, you dont need to provide different base address for softmax, as softmax is part of DPU IP itself [till DNNDK flow, DPU version 3.2, in Vitis-AI flow it is different, i think ]. You are just enabling or disabling softmax from the IP customization option. The forum link you referred is for 2018.2 version of ZCU102 DPU TRD (DPU version 2.x i think) and the PG338 you are following is of DPU 3.2 which has number of changes on design flows.

For the best approach please follow same DPU version based PG338, UG1327, DPU IP file and BSP etc.

Regards,
krishna@logictronix.com
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Observer
Observer
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Registered: ‎08-10-2020

Thank you! This helped a little - sadly the link you posted is outdated (reyling on DNNDK)

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Explorer
Explorer
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Registered: ‎06-09-2015

DPU integration tutorial has not been updated then after, however all the steps are same on latest DPU and VIVADO/Petalinux toolchain. We have tested process till DPU 3.0. As after it Vitis flow come up. However PG338 (3.2) have pointed DNNDK and Vitis flow, so DPU integration's detail flow and PG338 still helps for DPU3.2 development, i think.

Regards,
krishna@logictronix.com
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Observer
Observer
72 Views
Registered: ‎08-10-2020

Yes, thank you still kinda sad that one has to go back to an old version to find information which cannot be found in the new version. The whole xilinx documentation is a mess.

But nevertheless, thank you very much!