I'm working on the demo given by Building a Vitis Ultra96V2 and MIPI Platform.
With vitis2020.1 and vivado2020.1
The error message shows when I build the hardware:
===>The following messages were generated while creating FPGA bitstream. Log file: /home/xz/Desktop/AI/files/build/workspace/hello_world/Hardware/dpu.build/link/vivado/vpl/runme.log :
ERROR: [VPL 41-1274] Set bus interface parameter, Value '1' is out of the range for parameter 'Data Width(DATA_WIDTH)' for BD Interface 'M_AXI_HPM0_FPD' . Valid values are - 32, 64
ERROR: [VPL 41-1273] Error running post_config_ip TCL procedure: ERROR: [Common 17-39] 'set_property' failed due to earlier errors.
::xilinx.com_ip_zynq_ultra_ps_e_3.3::post_config_ip Line 12
ERROR: [VPL 60-773] In '/home/xz/Desktop/AI/files/build/workspace/hello_world/Hardware/dpu.build/link/vivado/vpl/vivado.log', caught Tcl error: ERROR: [Common 17-39] 'set_property' failed due to earlier errors.
ERROR: [VPL 60-704] Integration error, Failed to update block diagram in project required for hardware synthesis.The project is 'prj'. The block diagram update script is '.local/dr.bd.tcl'. The block diagram update script was generated by system linker. An error stack with function names and arguments may be available in the 'vivado.log'.
ERROR: [VPL 60-1328] Vpl run 'vpl' failed
ERROR: [VPL 60-806] Failed to finish platform linker
INFO: [v++ 60-1442] [22:31:08] Run run_link: Step vpl: Failed
Time (s): cpu = 00:00:05 ; elapsed = 00:00:39 . Memory (MB): peak = 1346.258 ; gain = 0.000 ; free physical = 272 ; free virtual = 3573
ERROR: [v++ 60-661] v++ link run 'run_link' failed
ERROR: [v++ 60-626] Kernel link failed to complete
ERROR: [v++ 60-703] Failed to finish linking
INFO: [v++ 60-1653] Closing dispatch client.
makefile:82: recipe for target 'dpu.xclbin' failed
make: *** [dpu.xclbin] Error 1
This error is given by Vivado while "dr.bd.tcl" Is executing commands below:
#---------------------------
# Instantiating axi_ic_zynq_ultra_ps_e_0_M_AXI_HPM0_FPD
#---------------------------
set axi_ic_zynq_ultra_ps_e_0_M_AXI_HPM0_FPD [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_ic_zynq_ultra_ps_e_0_M_AXI_HPM0_FPD]
set_property -dict [ list \
CONFIG.NUM_MI {1} \
CONFIG.NUM_SI {1} \
CONFIG.M00_HAS_REGSLICE {0} \
CONFIG.S00_HAS_REGSLICE {0} ] $axi_ic_zynq_ultra_ps_e_0_M_AXI_HPM0_FPD
This error can be reproduce by adding "M_AXI_HPM0_FPD" port in Vivado manually by customizing the IP core:
And the error message is:
Which is exactly the same as the error before.
However, this error message does not cause any problem in Vivado. If I run "validate design" in the block design window, this error will disappear.
Plus, this error will only happen when this port is enabled for the first time, if I disable it and enable it again, this error message won't appear.
The problem is that this error message will cause a build failure in Vitis!
I think this is a bug for Vivado. Any ideas to fix this problem?