How to generate dpu.xclbin in vivado/vitis flow?

[lxfy1220]

When I try to run a yolo3 application in vivado flow using dpu v3.2 IP core, dpu.xclbin cannot be generated. I read seversal post in this board and notice that vitis flow is the recommended way.

I wonder if I use vivado to add DPU IP core and export .xsa to vitis, whether dpu.xclbin can be generated?

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I am a newbie in FPGA development. Thanks a lot for your help.

[meherp · Accepted solution]

HI @lxfy1220 

The dpu.xclbin is generated as an output file when we create the application in the Vitis flow, as shown below, 

Below is the tutorial which contains the complete process for creating the application.

https://github.com/gewuek/vitis_ai_custom_platform_flow

[lxfy1220]

HI @meherp 

Thank you for your reply. From the tutorial I find the DPU IP core must  be added in vitis. Is it necessary? I use vivado and vitis in windows before. Should I switch to the Linux？ 

[meherp]

The examples uses the Petalinux environment, therefore we will need the Linux machine. 

Yes we need to add the DPU IP in Vitis project ( the connection between DPU IP and Vivado project is completed in the Vitis)

[lxfy1220]

Okay，thank you for your answer. It really helps me a lot. I'll change my develop environment.