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anz162112
Contributor
Contributor
445 Views
Registered: ‎07-05-2018

Implementing more than 3 DPUs

Hi,

I wan to build more than 3 DPUs for ZCU102. If I take 512 DPU, I can implement up to 8 DPUs on ZCU102. I built the vitis project with 8 512 DPUs. When I check on board using explorer, I see only 3 DPUs. Can anyone tell me what are changes I need to make to implement 8 DPUs of 512?

Regards,
Shikha Goel
(Ph.D. , IIT Delhi)
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5 Replies
jheaton
Xilinx Employee
Xilinx Employee
378 Views
Registered: ‎03-21-2008

I do not recommend using more than 3 DPUs on the ZCU102 regardless of the DPU size. You are going to run into memory BW utilization issues if they all run simultaneously, and will probably not see a performance increase vs, using 3 DPUs.

Is there a reason you wanted to use more than 3? You can target multiple models to the same DPU.

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anz162112
Contributor
Contributor
329 Views
Registered: ‎07-05-2018

Dear Sir,

But this may not be true. Because we have seen that different CNNs have different bandwidth requirements. Also, as we go to smaller DPU sizes, we see that bandwidth requirement in smaller DPU sizes is less as compared to larger DPU sizes. So, based on this, if we increase the DPU number for smaller DPU sizes like 512, the more number of DPUs should be able to see some performance bandwidth.

I am attaching the screenshot as well. The graph shows the bandwidth requirement for different CNNs across different DPU sizes. This data is taken from the profile tool of DPU.

I am also referring to our paper where we show the effect of interference on the runtime. We are able to show that for smaller DPU sizes, we can see further performance improvement if we increase the number of DPUs for smaller DPU size. Through our estimation tool, we can predict the runtime for increased number of DPUs. 

Shikha Goel, Rajesh Kedia, Rijurekha Sen and M. Balakrishnan. "INFER: INterFerence-aware Estimation of Runtime for Concurrent CNN Execution on DPUs". In International Conference on Field Programmable Technology (FPT), 2020.

Regards,
Shikha Goel
(Ph.D. , IIT Delhi)
chart.png
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anz162112
Contributor
Contributor
265 Views
Registered: ‎07-05-2018

Can any help be provided on the same? Is there anyone who could implement more than 3 DPUs and help me through the workflow. I need this urgently for my work for deep analysis.

Regards,
Shikha Goel
(Ph.D. , IIT Delhi)
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joebrt
Participant
Participant
117 Views
Registered: ‎05-07-2019

Hello,

I was wondering if you received an answer on this? I'm very curious as to what can/cannot be implemented

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anz162112
Contributor
Contributor
74 Views
Registered: ‎07-05-2018

I am still stuck on this issue.

Regards,
Shikha Goel
(Ph.D. , IIT Delhi)
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