Insufficient Resources for DPU on ZCU104 After Synthesis

[asobeih]

Hi,

I am trying to implement a Dual DPU Cores of architecture B4096 on ZCU104 FPGA in order to report resources utilization and power consumption. I know there is a ready-to-use image available to download on Xilinx AI Developer Hub, which implements the same dual DPU cores of the same architecture and features.

However, when I synthesize the design, it results in LUT count and LUTRAM that exceed the available resources on the FPGA. How to solve this?

In a few words, my goal is to calculate the resources utilization and power consumptions of the DPU cores used in this image (I am attaching an image of the output of command "dexplorer -w" to show the DPU configurations:

https://www.xilinx.com/bin/public/openDownload?filename=xilinx-zcu104-dpu-v2020.1-v1.2.0.img.gz

I am using Vivado 2019.1. I tried the default synthesis strategy and Flow_AreaOptimized_High strategies. Both resulted in the same problem of insufficient resources problem in spite of the fact that the same exact DPU cores are already implemented on the image I mentioned earlier.

 

[asobeih]

Hi,
I still have not got any reply yet. Would anyone please help me?

Thanks.

[dsp81]

I see a few potential issues

1. The pre-built ZCU104 image you are using was generated with the 2020.1 tools, which means it was built with a newer version of the DPU IP.  You are using the 2019.1 tools and version 3.0 of the DPU IP.  There will most likely be resource differences between the two version of the IP.  This is not something that should cause a build issue, just something to be aware.
2. The IP configuration you are using specifies 1 softmax core, but the pre-built ZCU104 SD card image does not have softmax in the PL.

I would recommend disabling the softmax core and see if that fixes your issue.