08-24-2020 09:20 AM - edited 08-24-2020 10:29 AM
I am trying to implement a Dual DPU Cores of architecture B4096 on ZCU104 FPGA in order to report resources utilization and power consumption. I know there is a ready-to-use image available to download on Xilinx AI Developer Hub, which implements the same dual DPU cores of the same architecture and features.
However, when I synthesize the design, it results in LUT count and LUTRAM that exceed the available resources on the FPGA. How to solve this?
In a few words, my goal is to calculate the resources utilization and power consumptions of the DPU cores used in this image (I am attaching an image of the output of command "dexplorer -w" to show the DPU configurations:
I am using Vivado 2019.1. I tried the default synthesis strategy and Flow_AreaOptimized_High strategies. Both resulted in the same problem of insufficient resources problem in spite of the fact that the same exact DPU cores are already implemented on the image I mentioned earlier.
09-04-2020 07:30 AM - edited 09-09-2020 11:59 AM
I see a few potential issues
I would recommend disabling the softmax core and see if that fixes your issue.