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justinf22
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Registered: ‎09-20-2020

Naming question

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Hello, I'm trying to get a general lay of the land of AI acceleration frameworks on Xilinx FPGAs. I understand that Vitis is a high level frame work to allow deploying models to Xilinx hardware for acceleration. However I am somewhat confused by the bitstream/IP naming. My understanding was DPU was the set of IP cores for AI inference acceleration on embedded systems and xDNN was the IP core for inference acceleration on Alveo cards with an x86 host CPU. But it looks like the documentation now refers to use of DPU IPs with Alveo cards. Is this just a renaming or is there a fundamental difference between xDNN and DPU that I am missing? Thanks.

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jasonwu
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Registered: ‎03-27-2013

Hi @justinf22 ,

 

The white paper is for xDNN/ML-Suite. So it could be a reference for U200/U250 in VAI 1.2, not for MPSoC or U50.

 

Best Regards,
Jason
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jasonwu
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Registered: ‎03-27-2013

Hi @justinf22 ,

 

I think your understanding is correct.

For now U200 and U250 are using legency ML-suite solution. That should be the xDNN you can see on the document.

And for U50 and U280 the DPU like architecture is used. And U200/U250 would use same Arch in the future.

 

Best Regards,
Jason
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justinf22
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Registered: ‎09-20-2020

Okay cool that's definitely helpful. My only remaining question is if the whitepaper linked on the Vitis-AI github (https://www.xilinx.com/support/documentation/white_papers/wp504-accel-dnns.pdf) is still relevent to Vitis and the DPU IP as it seems to refrence xDNN and the xfDNN software stack. Are these products completely different from Vitis or are these performance metrics still relevant to Vitis?

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jasonwu
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Registered: ‎03-27-2013

Hi @justinf22 ,

 

The white paper is for xDNN/ML-Suite. So it could be a reference for U200/U250 in VAI 1.2, not for MPSoC or U50.

 

Best Regards,
Jason
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justinf22
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Registered: ‎09-20-2020
Fantastic, thank you.
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