07-31-2020 09:59 AM
I have a Vitis project, that is built from the zcu104_dpu platform. The DPU_TRD has been followed, and I have a dpu.xo file.
My project is running in Vitis, and I am trying to use refineDet. I am using the refinedet_pruned_0_8 model.
I have added my hardware accelerated functions into the Vitis project, and the only one I have is dpu_xrt_top
I have the number of compute units set to 2, but I have also tried it with 1.
After a while of the build running, I receive the following errors:
VPL UTLZ-1] Resource utilization: RAMB18 and RAMB36/FIFO over-utilized in TOp Level Design (This design requires more RAMB18 and RAMB36-FIFO cells than are available in the target device. This design requires 641 of such cell types but only 624 compatible sites are available in the target device.
[VPL 4-23] Errors(s) found uring DRC. Placer not run.
I'm not doing anything incredibly out of the ordinary I dont believe, since I have based all of my code from the Xilinx Vitis AI samples.
Any insight ?
08-02-2020 05:33 PM
Hi @kdavis119 ,
To create a custom platform? You may refer to this articule. I have successfuly deply VAI 1.2 on ZCU104 and record my steps there:
08-03-2020 06:29 PM
Hi @kdavis119 ,
Yes, this is just an option.
If you can't find a ZCU104 based platform can work you could try with this tutorial.
08-03-2020 06:53 PM
I think you may try changing the RAM usage configuration of DPU.
There are two options of RAM usage. High RAM Usage means that the on-chip memory block will be larger, allowing the DPU more flexibility to handle the internediate data. If the RAM is limited, Please define the low RAM Usage.
RAM Usage High : `define RAM_USAGE_HIGH
RAM Usage Low : `define RAM_USAGE_LOW
08-04-2020 05:59 AM
I'm sorry but I don't see how this would help me. I can compile other neural networks (like ssd) fine, it seems refineDet is the one causing the problems at the moment.
08-04-2020 06:01 AM
In our dpu_conf.vh file, I currently have my settings set to RAM_USAGE_HIGH.
Previously, I have been unable to meeting timing when building the DPU-TRD on the 104 board if my ram setting was set to RAM_USAGE_LOW
I am using a standard zcu104 development board. Does this setting need to be set to low for this board, and thus I need to investigate the timing issues I've seen with that setting ?
08-05-2020 05:25 AM
The resource utilization depends on your acceleration function. On top of the platform, different hw functions occupy different resources. For timing issues, RAM utilization is not the one and only tactic. You may try out other implementation strategies.