11-21-2020 08:28 AM
I am using this DPU image that runs on the ZCU104 board.
The DPU cores implemented in this image have the specifications shown in the below image:
When I try to synthesize the DPU TRD applying these specifications, I end up having that the required resources exceed the resources available on the FPGA. I use Vivado 2020.1, and I follow the same steps demonstrated in the Userguide. I tried different synthesis strategies.. Same result.
I just need someone to help me with either the complete resources utilization and power reports or to solve this issue I am facing to smoothly and successfully generate these reports myself!