Xilinx model zoo - DPU architecture dependent

[deepg799]

Hello all,

I hope all are doing great.

I have download the tf_vgg16/19 models from the Xilinx model zoo and tried to compile it for the two different DPU architecture B3136 & B4096 by using the vai_c_tensorflow compiler.

Result:

Vgg16/19 is successfully compiled for 4096 DPU architecture but it did not get compiled with 3136 DPU architecture with the following error.

(vitis-ai-tensorflow) root@root:/opt/vitis_ai/compiler$ ./vai_c_tensorflow -f /workspace/models/tf_vgg19_imagenet_224_224_39.28G/quantized/quantize_results
deploy_model.pb -a /workspace/dcf/evk.json -o /workspace/models/tf_vgg19_imagenet_224_224_39.28G/ -n vgg_19_tf
**************************************************
* VITIS_AI Compilation - Xilinx Inc.
**************************************************
/workspace/dcf/evk.json
[VAI_C-BACKEND][FATAL][/home/dnnc/submodules/asicv2com/include/Dpu/DpuOp.imp:365][VALUE_UNMATCH][The value is not supposed!] 0: 2-24-31 Field is too long!
*** Check failure stack trace: ***

From the above experience I came to know that some of the model zoo networks are DPU architecture-dependent. 

It would be very useful for us If someone can provide the information about the Xilinx model zoo support with respect to the DPU architecture.

Thank you in advance.

[meherp]

HI @deepg799 

If you have an architecture other than 4096, then you need to recompile the frozen model. 

Please refer https://github.com/gewuek/vitis_ai_custom_platform_flow where .hwh file is used to recompile the model. 

Please refer https://forums.xilinx.com/t5/forums/replypage/board-id/AI/message-id/4346 where .hwh file is used to recompile the model. 

[deepg799]

@meherp 

Thanks for the update.

you provide the reference link to this forum only. could you reshare the reference link?

I think I am doing the same steps that you are telling here.

(vitis-ai-tensorflow) @root@root:/opt/vitis_ai/compiler$ ./vai_c_tensorflow -f /workspace/models/tf_vgg19_imagenet_224_224_39.28G/quantized/quantize_results/
deploy_model.pb -a /workspace/dcf/evk.json -o /workspace/models/tf_vgg19_imagenet_224_224_39.28G/ -n vgg_19_tf

**************************************************
* VITIS_AI Compilation - Xilinx Inc.
**************************************************
/workspace/dcf/evk.json
[VAI_C-BACKEND][FATAL][/home/dnnc/submodules/asicv2com/include/Dpu/DpuOp.imp:365][VALUE_UNMATCH][The value is not supposed!] 0: 2-24-31 Field is too long!
*** Check failure stack trace: ***

The evk.json file is pointing to .dcf file. which is generated by the ddump utility by using the .hwh file.

[meherp]

Hi @deepg799 

Updated in previous reply as well.

"Please refer https://github.com/gewuek/vitis_ai_custom_platform_flow where .hwh file is used to recompile the model."

[deepg799]

@meherp 

Thanks for the update.

Even they are also doing in same way who I am trying to do.

Please let me know if you have any solution for the above issue. As I also told I can able to recompile the model for 4096 but it is not for 3136 Arch.

[deepg799]

@meherp 

It seems vgg16/19 is not supported by the B3136 DPU architecture.

[deepg799]

Does anyone have any suggestions over here?

is the xilinx model zoo is compatible with all the DPU architecture?

[meherp · Accepted solution]

HI @deepg799 

Some of the large models may fail in architectures other than 4096. 
VGG is one of the large model. May be you can try the resnet model which has better efficiency, and have less number of parameters than VGG.