UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Visitor aidan.wenzel
Visitor
788 Views
Registered: ‎07-05-2018

AXI DMA from Linux Issue - IOC_Irq Flag + Idle Set After Setting Transfer Length

I have implemented a simple DMA testing FPGA and am attempting to drive the transfer from Linux using the memory mapped registers of the device. My program follows the following flow:

1) Reset MM2S and S2MM by setting the control registers to 4

2) Halt DMA by setting control registers to 0

3) Write source and destination physical addresses

4) Start channel with masked interrups by setting control to 0xf001

5) Write transfer lengths to both channels

6) Wait for both channels to read IOC_Irq showing completion

 

The program runs the first two times without issue, successfully transferring all the way through the loop. On the third (and every run after) run it hangs, with the MM2S stream reading "running idle IOC_Irq" in the status register after writing the length to that channel.

 

I've attached the code I'm running, as well as images showing the runs. What could cause this sort of problem?

Tags (4)
0 Kudos
8 Replies
Xilinx Employee
Xilinx Employee
728 Views
Registered: ‎10-04-2016

Re: AXI DMA from Linux Issue - IOC_Irq Flag + Idle Set After Setting Transfer Length

Hi @aidan.wenzel,

Does either channel report an error when you are in the stuck condition? (Are Dly_Irq or Err_Irq asserting rather than IOC_Irq?)

Regards,

Deanna

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
0 Kudos
Visitor aidan.wenzel
Visitor
696 Views
Registered: ‎07-05-2018

Re: AXI DMA from Linux Issue - IOC_Irq Flag + Idle Set After Setting Transfer Length

Hi Deanna, 

I finally got an error to display in one of my runs today: 

MM2S Status: halted DMADecErr IOC_Irq Err_Irq

But when I ran it again (3rd run) after rebooting the board I was back to the status I got in previous runs - running idle IOC_Irq

0 Kudos
Visitor aidan.wenzel
Visitor
683 Views
Registered: ‎07-05-2018

Re: AXI DMA from Linux Issue - IOC_Irq Flag + Idle Set After Setting Transfer Length

Just tested using separate buffers (instead of repeating the same source and dest) and with all DMA transactions taking place in the same program, still get this behaviour. The third DMA transaction always results in the MM2S channel stalling out with the status bits set for "running idle IOC_Irq". 

Worth noting, those are the proper status bits for completion. So that makes me think that the MM2S channel actually behaved properly and succeeded in a write out, but the S2MM channel failed to read back in. Not sure if that guesswork helps at all. The S2MM channel is stuck on "running". 

Would the Vivado project be helpful? 

0 Kudos
Xilinx Employee
Xilinx Employee
680 Views
Registered: ‎10-04-2016

Re: AXI DMA from Linux Issue - IOC_Irq Flag + Idle Set After Setting Transfer Length

Hi @aidan.wenzel,

A picture of the block diagram would help. Do you have M_AXIS_MM2S tied to S_AXIS_S2MM (loop back mode) or is there an IP in the middle?

I would be interested in adding System ILAs to the M_AXI_MM2S, M_AXIS_MM2S, S_AXIS_S2MM and M_AXI_S2MM interfaces to see how far the AXI DMA engine gets in that third transfer. 

Regards,

Deanna

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
0 Kudos
Visitor aidan.wenzel
Visitor
663 Views
Registered: ‎07-05-2018

Re: AXI DMA from Linux Issue - IOC_Irq Flag + Idle Set After Setting Transfer Length

Deanna, 

I've attached a picture as well as a script for the block design. 

Thank you for your help! 

-Aidan 

vivado_2019-03-27_08-45-12.png
0 Kudos
Xilinx Employee
Xilinx Employee
654 Views
Registered: ‎10-04-2016

Re: AXI DMA from Linux Issue - IOC_Irq Flag + Idle Set After Setting Transfer Length

Hi @aidan.wenzel,

I think the next step would be to add ILAs to your design and try to trigger on the third transfer. It's not clear where the transfer is getting stuck. 

Another thought: when you issue the soft reset, do you poll to see that the reset has completed before continuing to set up the transfer?

Regards,

Deanna

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
0 Kudos
Visitor aidan.wenzel
Visitor
627 Views
Registered: ‎07-05-2018

Re: AXI DMA from Linux Issue - IOC_Irq Flag + Idle Set After Setting Transfer Length

So I've now demonstrated that it has something to do with the number of bytes written in/out. Even over separate runs, it looks like once more than 64 bytes have been looped through the system that is when it begins to hang. If you try to write more than 64 bytes even on the first run it fails. 

 

0 Kudos
Xilinx Employee
Xilinx Employee
620 Views
Registered: ‎10-04-2016

Re: AXI DMA from Linux Issue - IOC_Irq Flag + Idle Set After Setting Transfer Length

Hi @aidan.wenzel,

Is this the same failure or a different failure?

The upside of hardening the failure is that this makes it easier to capture a trace of the hardware interfaces to see where the data is getting stuck.

Regards,

Deanna

 

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
0 Kudos