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Adventurer
Adventurer
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Registered: ‎12-26-2016

AXI DMA holds data two cycles long

Hi there,

I'm using Vivado 2018.2 and developing for a Zynq020. I got data in my DDR memory and want to transfer it into the PL; for that a DMA with AXI SmartConnect on the Zynq PS HP0 is used, memory map and stream width are both set to 32 bit. DMA burst size is 32 words. If I capture the AXI-MM and AXI-S signals with the ILA core I got the following:

DMAILA.png

The data I've written to the DDR is {131071; 0; 32767; 0 -131071; 0 ; 0 ;-32767; 131071}. This is double checked. I use Linux Ubuntu 12 as an OS on the Zynq. The program is cross-compiled with the arm-linux-gnueabihf-g++ toolchain provided by Xilinx SDK 2018.2

Here is my board design system setup:

SystemSetup.png

Are there any possibilities that I've misconfigured something? I used the same setup on Vivado 2017.4 and my design was running.

If you need more information just let me know :)

Cheers
Thomas

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DMAILA.png
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Highlighted
Adventurer
Adventurer
463 Views
Registered: ‎12-26-2016

It's working if I change the AXI HP0 port width from 32 to 64. The rest remains exactly the same. If I compare the AXI standard to the transactions I've observed there is quite some behaviour unclear to me. In a nutshell:

  • The data is 32 bit aligned and 32 bit width
  • AXI DMA is configured as 32bit stream and 32bit memory map
  • There is a smart connect between DMA and Zynq HP0

When the HP0 width is configured as 32 bit the AXI signal (on the DMA MM side) arsize signal is 0b010 (4 bytes transfer), arburst is 0b01 (incrementing read address). But only every second 32 bit word is on the stream but hold two samples (see above).

If I change the HP0 width to 64 bit the data is valid and consistent to the DDR memory.

Does anyoe know?

Thanks in advance
Thomas

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