11-14-2018 07:12 AM
I have a HW design on ZCU102 that is implementing an AXI DMA loopback.
So I'm using an AXI DMA IP and I have the M_AXIS interface connected to the S_AXIS interface. I'm using a DMA proxy driver that issues DMA reads and Writes at the "same" time. My test application works well for looping data back. I am now trying to put a processing block in the middle of the loopback, and my performance takes a nosedive and other bad things are occurring. I've added AXIS Data Fifos on both/either sides of the processing block, and I still see my performance fall apart. Looking at my Zynq console, the DMA Receive transaction is timing out.
What I'm pretty sure is occurring, is the processing block has a ton of latency, and so until it outputs data, the DMA receive datapath (S_AXIS_S2MM) is not flowing data and thus the DMA rx is blocked.
How do AXI-Stream based processing chains deal with this sort of situation. I find myself wanting to implement basically an register(with S_AXIS and M_AXIS interfaces) that dumps out zeros until I know that the data from my processing block has started, and once that has occurred, switch in the output from my processing block. I'd have to look at a TUSER signal or perhaps the TLAST signal from the output of my processing block.
I know the correct answer for a proper design is better and more granular control in the DMA proxy driver, but until I get that in place, is there not a xilinx prebuilt AXI-Stream unblocker / conditional-zero-stuffer?
11-30-2018 01:40 PM
You might be able to use the AXI Traffic Generator as a band-aid for now. My feeling is that it will probably introduce more problems than focusing your attention on improving the proxy driver.