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Visitor
Visitor
1,217 Views
Registered: ‎11-21-2018

AXI DMA stream data width is always 32 bits in Vivado 2018.2

I have data coming from custom IP connected to S2MM interface of AXI DMA. Data size is 96 bits. I have included a FIFO before the DMA. Now, there is a mismatch between the data out from FIFO (size = 96 bits) and the s2mm_tdata size. The s2mm_tdata size is always fixed to 32 bits. How to change the size to 96 bits so that there is no size mismatch between output of FIFO and Input to DMA?

Validating the design throws the critical warning:

 [BD 41-237] Bus Interface property TDATA_NUM_BYTES does not match between /axi_dma_1/S_AXIS_S2MM(4) and /axis_sfifo/m(12)

and an error:       [xilinx.com:ip:axi_dma:7.1-8] /axi_dma_1
                   #################################################################################
                   Propagated TDATA WIDTH on S_AXIS_S2MM is not 8, 16, 32, 64, 128, 256, 512 or 1024
                   #################################################################################

Kindly refer the screenshots.

 

FIFO_DMA.png
DMA_Settings.png
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Moderator
Moderator
1,125 Views
Registered: ‎06-29-2011

Hi @echoonezero

This error and warning is indicating that you are not using one of the supported data widths for the AXI DMA.

From PG021:

image.png

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Don’t forget to reply, kudo, and accept as solution.
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Kind regards,
Gareth