12-14-2018 03:43 AM
In my project i need to add my custom logic into Block Diagram which is controlled by Zynq ARM . So i need to add AXI-Lite signal to configure my custom logic register. I searched the AXI IPIF IP topic in xilinx forums. but i don't known how to use it as well as which is a hidden IP. So my question is
What are the procedure to use IPIF and how to add my custom logic into IPIF.
There are procedure for How to Create and Package IP in the Vivado. But I need IPIF based configuration. I am using Vivado 2018.1.
12-19-2018 08:33 AM
In the Vivado menu bar, select "Tools" -> "Create and Package New IP...":
Choose "Create AXI4 Peripheral":
Configure the peripheral to contain the AXI-Lite interface(s) that you need:
Once the tool creates the framework files, update them with your custom logic.
After updating the HDL files, repackage the IP so you can place it in a Vivado IPI block diagram.
If you haven't already done so, get a copy of the AXI spec:
12-24-2018 05:31 AM
01-10-2019 04:50 AM
The following AR provided files for the deprecated AXI IPIF helper IPs.