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Adventurer
Adventurer
806 Views
Registered: ‎03-08-2018

AXI IPIF Problem

Hi,

               In my project i need to add my custom logic into Block Diagram which is controlled by Zynq ARM . So i need to add AXI-Lite signal to configure my custom logic register. I searched the AXI IPIF IP topic in xilinx forums. but i don't known how to use it as well as which is a hidden IP. So my question is

What are the procedure to use IPIF and how to add my custom logic into IPIF. 

There are procedure for How to Create and Package IP in the Vivado. But I need IPIF based configuration. I am using Vivado 2018.1.

Thanks

kannan

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4 Replies
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Scholar
Scholar
741 Views
Registered: ‎02-01-2013

 

In the Vivado menu bar, select "Tools" -> "Create and Package New IP...":

2018-12-19_11-09-02.jpg

Choose "Create AXI4 Peripheral":

2018-12-19_11-09-46.jpg

Configure the peripheral to contain the AXI-Lite interface(s) that you need:

2018-12-19_11-11-11.jpg

Once the tool creates the framework files, update them with your custom logic.

2018-12-19_11-24-26.jpg

After updating the HDL files, repackage the IP so you can place it in a Vivado IPI block diagram.

If you haven't already done so, get a copy of the AXI spec:

https://developer.arm.com/products/architecture/system-architectures/amba/amba-4

-Joe G.

 

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Adventurer
Adventurer
710 Views
Registered: ‎03-08-2018

Hi,

                Thank you for your response. but i want to use IPIF in my project.

Thanks

kannan

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Scholar
Scholar
696 Views
Registered: ‎02-01-2013

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Moderator
Moderator
604 Views
Registered: ‎06-29-2011

Hi @kannan

The following AR provided files for the deprecated AXI IPIF helper IPs.

AR:62549 - https://www.xilinx.com/support/answers/62549.html

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Kind regards,
Gareth