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Observer
Observer
1,044 Views
Registered: ‎03-22-2019

AXI Stream Switch with DMA

Hello,

iam trying to make my HW more configurable, so that i can choose between two Calculation IPs. My system looks like this.

System.PNGConfig_Axis_Switch.PNG

I wanna choose with the AXIS Switch which values should be send to the DMA, either from test1 or from test3. If i wire just one test core back to my dma it works, but with the AXIS Switch it doesnt. I get a DMA Timeout then. Above there is also my Configuration of the AXIS Switch. I choose controll register to choose which Datas from which Test Core should be send. To controll this i used those functions. With that Code i wanna route the Test1 Data of my Slave 0 to the Master Port.

int MiIndex=0;
int SiIndex=1;

XTest_Initialize(&IPTest);
XTest3_Initialize(&IPTest2);
XAxis_Initialize_Linux(&StreamDown);

XAxisScr_RegUpdateDisable(&StreamDown);

XAxisScr_MiPortDisableAll(&StreamDown);

XTest_Set_gain(&IPTest, gain);
XTest3_Set_gain(&IPTest2, gain);

XAxisScr_MiPortEnable(&StreamDown,MiIndex,SiIndex);

XAxisScr_RegUpdateEnable(&StreamDown);

XTeat_Start(&IPTest);
//XTest3_Start(&IPTest2);

XTest_EnableAutoRestart(&IPTest);
//XTest3_EnableAutoRestart(&IPTest2);

//End of Initalizing the IP Core

 

I have to say iam using the DMA in Interrupt Mode.

I also tried work around that with implementing my own Switch Stream, but even this doesnt work. I attached my HLS file of that.

I hope someone could help me.

 

 

 

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Xilinx Employee
Xilinx Employee
951 Views
Registered: ‎10-04-2016

Hi @yannik.rink ,

Can you peek/poke the AXI Stream Switch registers to verify that they are configured as you expect? Given the configuration, the IP should only have two registers.

Alternatively, can you run the XAxisScr_IsMiPortEnabled driver function to verify that the AXI Stream Switch is set up as expected?

Regards,

Deanna

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Observer
Observer
927 Views
Registered: ‎03-22-2019

Hi @demarco ,

I changed my System to a System were iam using the Axi Switches from the Xilinx Libary. 

My Systems look like the attached picture now. The AXI Switches worki as expected.

After 250 DMA Transfers I get following message: Unable to prepare the dma engine for the DMA transmit buffer

I guess I have some issue in my ownmade IP Cores. This is how my HLS Application look like:

typedef ap_axis <32,1,1,1> AXI_T;
typedef hls::stream<AXI_T> STREAM_T;

void test2(STREAM_T &A, STREAM_T &B){

#pragma HLS INTERFACE axis port=A
#pragma HLS INTERFACE axis port=B
#pragma HLS INTERFACE ap_ctrl_none port=return

AXI_T tmpA, tmpB;

int LEN=5000;

for(int i=0; i<LEN; i++){

#pragma HLS PIPELINE

    A >> tmpA;

    tmpB.data=tmpA.data+tmpA.data;
    if(i == LEN-1){
		tmpB.last = 1;
	}
    tmpB.keep = 0xf;
	B << tmpB;

}

}

Do you see any problem in this?

 

 

 

System.PNG
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Observer
Observer
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Registered: ‎03-22-2019

I forgot my Settings for the DMA Core are:

Width of buffer: 26 Bits-> Should be more than enough, because i only transfer 5000 32 Bit values
Address Width: 64 Bits
Memory Map Data Width: 64
Stream Data Width: 32
Burst Size:256
Allow Unaligned Transfers and enable Scatter gather are checked.

 

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Xilinx Employee
Xilinx Employee
910 Views
Registered: ‎10-04-2016

Hi @yannik.rink ,

Could you start a new thread on the Design Tools -> HLS board for your most recent question?

The error suggests something is going wrong with the allocation of the buffer descriptor on your 251st loop. I'm not sure how to correlate this to your HLS code.

Regards,

Deanna

 

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