AXI Stream in Microblaze

[soccerchamp]

Hi all,
I am creating a Micoblaze based  design in Vivado 2018.2 targetting Virtex Ultrascale FPGA. I want to use one AXI stream channel in Microblaze (one Master and one slave). Can anybody point me some example firmware code which use AXI stream interface?

I mainy need below information.

WIth M_AXI_DP port, I can use Xil_out32 and Xil_In32 functions to write and read 32 bit data from an Address. What are the equivalant finctions for AXI Stream transfers? Which file should I include to access those funcrions? (like xil_io.h)

[abouassi]

Hi @soccerchamp,

You can refer to this Wiki_article which contains a design that use Microblaze stream interface and an SDK demo project.
Also you can refer to this Forum_thread.

[soccerchamp]

@abouassi 

Thanks for your reply. It really helped.

I have one more clarification. Is it possible to run the stream interface with a differnt clock with respect to microblaze clock?

Regards

Anoop