06-16-2019 11:55 PM
I am creating a Micoblaze based design in Vivado 2018.2 targetting Virtex Ultrascale FPGA. I want to use one AXI stream channel in Microblaze (one Master and one slave). Can anybody point me some example firmware code which use AXI stream interface?
I mainy need below information.
WIth M_AXI_DP port, I can use Xil_out32 and Xil_In32 functions to write and read 32 bit data from an Address. What are the equivalant finctions for AXI Stream transfers? Which file should I include to access those funcrions? (like xil_io.h)
06-21-2019 04:30 AM
06-25-2019 11:56 PM - edited 06-26-2019 12:04 AM