Vivado always give the CRITICAL WARNING, when create HDL wrapper, this CRITICAL WARNING as follow show:
CRITICAL WARNING: [xilinx.com:ip:smartconnect:1.0-1] ddr3_smartconnect_0_2: The device(s) attached to /S00_AXI do not share a common clock source with this smartconnect instance. Re-customize this AXI SmartConnect instance to add a new clock pin and connect it to the same clock source of the IP attached to /S00_AXI to prevent futher clock DRC violations.
This issue is generated by Vivado when you're using different clocks in your design. This clocks are relates to the blocks associated with the axi smartConnect block. To solve this warning modify your AXI SmartConnect adding a new clock port. I attach a screenshot showing a scenario where this solution is valid . I hope solve to you this warning.