02-24-2018 03:11 PM - edited 02-24-2018 03:16 PM
I have an AXI4 MM interface of which I'm the master.
The data that I want to write to the slave is buffered in a FIFO.
To achieve better timing - I wanted to use a FIFO with a registered output...but it seems impossible with AXI4 MM.
Explaining my point:
Suppose I assert AWVALID all the time and wait for the slave to asset AWREADY.
When the slave asserts AWREADY - I issue a read command to the FIFO to bring new data for the next clock.
This will work well if the FIFO has an unregistered output...but if the output of the FIFO is registered (as it's usually desired) - the slave will receive wrong data.
What am I missing?
02-25-2018 10:28 PM
To have better timing by adding an additional pipe-line, use AXI Register Slice IP.
Manually inserting Flip-Flops on the AXI signal may lead to violation of AXI protocol.
03-02-2018 02:56 PM
You want to use a FIFO that has first word fall through mode and supports registered outputs. This will ensure that the data presented on dout will be valid (assuming it's not empty) when read enable is asserted. xpm_fifo (found in the language templates of Vivado) supports this feature, and so does FIFO Generator. You would want to configure the xpm_fifo for "FWFT" read mode which will register the output of the FIFO and provide a read latency of 0.
03-04-2018 02:17 AM - edited 03-04-2018 02:23 AM
How can I configure an XPM FIFO to have output registers ?
Is it done via changing the "FIFO_READ_LATENCY" generic ?