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Voyager
Voyager
567 Views
Registered: ‎04-12-2012

AXI4 MM - using a FIFO with a registered output

Hello,

 

I have an AXI4 MM interface of which I'm the master.

The data that I want to write to the slave is buffered in a FIFO.

To achieve better timing - I wanted to use a FIFO with a registered output...but it seems impossible with AXI4 MM.

 

Explaining my point:

Suppose I assert AWVALID all the time and wait for the slave to asset AWREADY.

When the slave asserts AWREADY - I issue a read command to the FIFO to bring new data for the next clock.

This will work well if the FIFO has an unregistered output...but if the output of the FIFO is registered (as it's usually desired) - the slave will receive wrong data.

 

What am I missing?

 

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3 Replies
Xilinx Employee
Xilinx Employee
461 Views
Registered: ‎02-26-2014

Re: AXI4 MM - using a FIFO with a registered output

Hi,

 

To have better timing by adding an additional pipe-line, use AXI Register Slice IP.

Manually inserting Flip-Flops on the AXI signal may lead to violation of AXI protocol.

 

Regards,

Ravi

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Xilinx Employee
Xilinx Employee
423 Views
Registered: ‎02-10-2015

Re: AXI4 MM - using a FIFO with a registered output

You want to use a FIFO that has first word fall through mode and supports registered outputs.  This will ensure that the data presented on dout will be valid (assuming it's not empty) when read enable is asserted.  xpm_fifo (found in the language templates of Vivado) supports this feature, and so does FIFO Generator. You would want to configure the xpm_fifo for "FWFT" read mode which will register the output of the FIFO and provide a read latency of 0.

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Voyager
Voyager
413 Views
Registered: ‎04-12-2012

Re: AXI4 MM - using a FIFO with a registered output

How can I configure an XPM FIFO to have output registers ?

Is it done via changing the "FIFO_READ_LATENCY" generic ?

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