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noobita
Visitor
Visitor
2,311 Views
Registered: ‎06-22-2019

AXI4-Stream Broadcaster Problem

Good afternoon,

Even though the title says "problem", after some readings here in the forum i understand that this is not a problem (it is for my application) of the AXI Broadcaster but how it is programmed.

My application is the following, i want to do a convolution in hardware, i have my IP done. Now, i want to have 4 IPs in the FPGA, each one recieving weights and data. The idea was to have one DMA channel sending the weights to all the IPs and then the same DMA sending data to one of the IPs and then 3 other DMAs sending data to each one of the rest of the 3 IPs. To be able to do so, i used a broadcaster, which has 5 outputs from the same DMA input: 2 connected to one IP and the other three connected to the other IPs (one output for each IP).

The problem of using the broadcaster for this application is that it waits for all the connected IPs to read its inputs (the output of the broadcaster). The objective was to have the 4 IPs reading the weights from the same DMA and then have each IP reading the data (which is different for each IP) from each DMA channel.

Since the use of the broadcaster is causing the application to stall and not moving forward, which block can i use to be able to achieve the intended objective? Is there a way in hls to disable a port or making it always tvalid? And by doing so would the broadcaster work and not stall?

Thanks for the help in advance.

Best regards

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2 Replies
demarco
Xilinx Employee
Xilinx Employee
2,249 Views
Registered: ‎10-04-2016

Hi @noobita,

You could try adding a FIFO between the AXI Broadcaster and the 3 "not ready" IPs. This should remove the backpressure that is causing your system to stall. It might take some experimentation to get the FIFOs sized correctly to meet your performance needs.

Take a look at the AXI4-Stream Data FIFO in PG085.

https://www.xilinx.com/support/documentation/ip_documentation/axis_infrastructure_ip_suite/v1_1/pg085-axi4stream-infrastructure.pdf

Regards,

Deanna

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florentw
Moderator
Moderator
2,230 Views
Registered: ‎11-09-2015

Hi @noobita 

I agree with @demarco, adding a FIFO should help.

This is a case I have covered in my Video Beginner Series 13: Using the AXI4-Stream Infrastructure IP Suite (Part 2). This is for video application but this can be applied to any type of application using the AXI4-Stream Brodcaster.

Hope that helps,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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