02-05-2019 06:23 AM - edited 02-05-2019 09:19 AM
I am trying to verify/simulate the correct behavior of a custom AXI4-Stream Master IP that I wrote without wizard. This custom IP should read data with a data rate smaller than the main clock, and transfer it to Slave.
To simulate its behavior (of course I am not 100 % sure of its correctness) I planned a simulation interfacing it with a AXI4-Stream Verification IP configured as Slave:
The testbench I wrote for this is the following:
`timescale 1ns / 1ps
module testbench(); reg aresetn; reg clk; reg data_clk; reg [31:0] data_in; reg [3:0] counter; wire [31:0] data_in_wire; wire data_clk_wire; wire clk_wire; wire aresetn_wire; wire tready_wire; wire [31:0] tdata_wire; wire [3:0] tkeep_wire; wire tlast_wire; wire tvalid_wire; assign data_in_wire = data_in; assign data_clk_wire = data_clk; assign clk_wire = clk; assign aresetn_wire = aresetn; RawToAXIStream_0 RawToAXIStream( .data_clk(data_clk_wire), .data_in(data_in_wire), .m00_axis_clk(clk_wire), .aresetn(aresetn), .m00_axis_tdata(tdata_wire), .m00_axis_tkeep(tkeep_wire), .m00_axis_tlast(tlast_wire), .m00_axis_tready(tready_wire), .m00_axis_tvalid(tvalid_wire) ); axi4stream_vip_0 axi4stream_vip( .aclk(clk_wire), .aresetn(aresetn_wire), .s_axis_tdata(tdata_wire), .s_axis_tkeep(tkeep_wire), .s_axis_tlast(tlast_wire), .s_axis_tvalid(tvalid_wire), .s_axis_tready(tready_wire) ); initial begin counter <= 0; clk <= 0; aresetn <= 0; data_clk <= 0; data_in <= 0; #3 aresetn <= 1; end // clock generation always begin #1 clk <= !clk; end always @(posedge clk) begin counter <= counter + 1; if(!counter) begin data_clk <= !data_clk; end end always @(posedge data_clk) begin data_in <= data_in + 1; end endmodule
But during the simulation I notice that the TREADY signal from the AXI4-Verification IP is always low:
Is this the correct way to make this kind of simulation ?
The Simulation languange is set as Mixed:
Could you please help to understand what I am doing wrong ?
02-08-2019 06:51 AM
The way that the Verification IPs (VIPs) are set up to require a few things. In PG277 (https://www.xilinx.com/support/documentation/ip_documentation/axi4stream_vip/v1_0/pg277-axi4stream-vip.pdf) it talks about the must-haves starting at page 29. There are two packages that are required which are not imported into your code, so I would start there.
I don't think the Mixed language is necessary if all of your design is in Verilog/SystemVerilog. Is your custom IP architected using VHDL?
In the product guide you will also see calls to start the master and slave transactions on the VIP through the VIP API. I would look into initiating a transaction from the VIP block through the API call, I think you may have just not "turned on" the VIP. Page 38 provides all the API calls for the VIP.
02-11-2019 03:25 AM
02-11-2019 08:19 AM
Sorry to confuse, but Verilog for your custom IP (and SystemVerilog for the testbench) should be the correct HDL to simulate with the Verification IP. I think your next step would be to use the APIs I talked about in my last reply which should start and utilize the Verification IP. I don't think you are telling the VIP to start or do anything in your testbench.
02-11-2019 08:45 AM
So it's not quiet clear to me how to use that API.
The PG277 says that I have to import some packages.
The Edit IP Window of my AXI Stream VIP links me to the following page:
I downloaded the ZIP file and I add the System Verilog sources to my simulation design (that's what I understand I have to do), but Vivado reports the API files as Syntax Error Files:
This seems to be quiet strange.
Of course the import directives in my testbench result in a error.
I am quiet confused on how to proceed.
02-11-2019 12:43 PM
Have you tried simulating even though the code says it has errors?
If it won't even simulate then I would look if there are any patches for the AXI Stream VIP packages (might have been a fix between versions).
Can you try these two things, and let me know if that changes anything?
02-11-2019 02:40 PM
In addition, can you try starting from the AXI4-Stream VIP Example Design? To open that it is best to open a design and insert the IP then right-click and click the button Open Example IP Design... This will give you an example testbench that sets up the VIP properly for a transfer. The product guide talks through how this example works, and then once that is setup properly you can edit that example to match what you want your testbench to do. Chapter 6 would be good to start from.
Using the files from that .zip shouldn't be necessary if you start from the testbench and associated files in the example design.
To further elaborate, you will need the Mixed language option set if you are using Verilog and SystemVerilog (as those are two seperate languages). SystemVerilog will be used for the testbench as some of the API calls used to start the VIP require SystemVerilog. Your actual design architected in Verilog is fine as the testbench should be able to work with a Verilog design.
02-12-2019 12:31 AM - edited 02-12-2019 12:32 AM
Thank you for your reply.
Yes, if I try to simulate the testbench with the syntaxs errors from Vivado, it fails with errors
If this is a Vivado error (I am using version 2018.3), I will be happy to see it working if it will be fixed.
The simulation of the AXI Stream VIP from the Example Design starts with no errors and I can see the transactions and I had no doubts about it.
I think that if I am unable to test the VIP with my custom IP, I can arrange this with from the Example Design. It's the best way for now.
02-12-2019 01:04 AM - edited 02-12-2019 01:19 AM
Have you checked in your custom code that you are driving the tvalid master signal correctly?
A master axi stream will set the tvalid and put the data package in the bus whenever it has data available independently of the slave tready signal state, and if tready is low the master will wait (keep tvalid set and the same data package in the bus) till the slave is ready to receive data (tready=1).
I can't see that behaviour in your simulation waveform.
02-12-2019 01:26 AM
A master axi stream will set the tvalid and put the data package in the bus whenever it has data available independently of the slave tready signal state,
Thanks, this is a detail I was missing and I also figured out from the VIP Example Design.
Thanks for ensuring it !
02-12-2019 08:18 AM
So you are able to start from the Example Design and then alter that to fit your custom IP and design?
I think the errors from before are because the files you imported from the .zip file are actually inside of Vivado already (no need to import them).
Are you able to continue on in order to simulate your custom IP? Has your issue been solved?
02-12-2019 09:01 AM - edited 02-14-2019 01:03 AM
No, I cannot say that I can easily plug my custom core inside the design and run the simulation without errors. Also, it's an API I don't know yet very well to solve this issue in a short time.
I think I will test my core straight into design. What I can say is that it behaves well with custom driven TREADY signal. It seems to do what it has to do...