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Participant leoeltipo
Participant
385 Views
Registered: ‎12-11-2017

Custom IP with multiple AXI slave interfases

Hello,

I am working on a Artix-7 design using Vivado 2018.2. I have created a custom IP with 2 AXI Lite slave interfases. When I export the hardware the hdf clearly shows two entries for my block, on for each register map, which are correct if I check in the Address Map view for block design. However, when I create my application and the bsp is created, the xparameters.h file does not have those two entries, it only shows one entry for my block. 

I have done different trials and looks like xparameters.h file generator will only add one entry per block, instead of one entry per interfase, as it should.

Am I missing something? Is there any way of having a IP with more that one AXI Lite slave and creating the xparameters.h correctly?

 

Thanks in advance,

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Xilinx Employee
Xilinx Employee
286 Views
Registered: ‎10-04-2016

Re: Custom IP with multiple AXI slave interfases

Hi @leoeltipo,

You aren't doing anything wrong, this is a known issue with the custom IP flow and how it defines the addressing parameters.

I am working on getting the AR published that explains how to work around this issue.

Regards,

Deanna

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